Methods and apparatus for controlling hierarchical cache memory

Details Methods and apparatus for controlling hierarchical cache memory Methods and apparatus for controlling hierarchical cache memory

2011-01-11

2011-01-11

Tsai, Sheng-Jen (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711SE12016

Reexamination Certificate

active

07870340

ABSTRACT:
Methods and apparatus for controlling hierarchical cache memories permit controlling a first level cache memory including a plurality of cache lines and controlling a next lower level cache memory including a plurality of cache lines. An additional memory may be associated with the next lower level cache memory and include a plurality of memory lines, the number of memory lines corresponding to the number of cache lines in a way set of the first level cache memory. Alternatively, the memory lines may include L-flags for multiple cache lines of each way set of the next lower level cache memory. L-flags associated with a given index plus any index offset from the first level cache memory may be contained in a single memory line of the additional memory.

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