Signal delay structure in high speed bit stream demultiplexer

Details Signal delay structure in high speed bit stream demultiplexer Signal delay structure in high speed bit stream demultiplexer

2011-01-04

2011-01-04

Liu, Shuwang (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S257000, C375S355000, C375S375000, C375S376000

Reexamination Certificate

active

07864909

ABSTRACT:
A signal delay structure and method of reducing skew between clock and data signals in a high-speed serial communications interface includes making a global adjustment to the clock signal in the time domain to compensate for a component of the skew that is common between the clock and all data signals. This can include skew caused by the variation in frequency of the input clock from a nominal value, misalignment between the phase of the clock and data generated at the source of the two signals. The global adjustment is made through a delay component that is common to all of the clock signal lines for which skew with data signals is to be compensated. A second level adjustment is made that compensates for the component of the skew that is common to the clock and a subset of the data signals.

REFERENCES:
patent: 6868504 (2005-03-01), Lin
patent: 6960948 (2005-11-01), Kizer et al.
patent: 7206956 (2007-04-01), Johnson et al.
patent: 2006/0129869 (2006-06-01), Hendrickson et al.

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