Circuit of on-chip network having four-node ring switch...

Details Circuit of on-chip network having four-node ring switch... Circuit of on-chip network having four-node ring switch...

2011-07-26

2011-07-26

Rinehart, Mark (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C370S221000, C370S222000, C370S223000, C370S224000, C370S258000

Reexamination Certificate

active

07987313

ABSTRACT:
A hierarchical ring architecture is constructed with on-chip networks. The on-chip network includes two type-0 ring nodes and two type-1 ring nodes. Multiple data transfer is provided in parallel between multiple processor cores or multiple functional units and register banks with a dynamic configuration. A low control complexity, an optimized local bandwidth, an optimized remote node path, a low routing complexity, and a simplified circuit is thus obtained.

REFERENCES:
patent: 4835763 (1989-05-01), Lau
patent: 5491686 (1996-02-01), Sato
patent: 6041036 (2000-03-01), Baek et al.
patent: 6526020 (2003-02-01), Ando
patent: 7031608 (2006-04-01), Chiaroni et al.
patent: 7782762 (2010-08-01), Xu

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