System for using partitioned masks to build a chip

Details System for using partitioned masks to build a chip System for using partitioned masks to build a chip

2011-01-11

2011-01-11

Lin, Sun J (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07870531

ABSTRACT:
A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A system is provided comprising a mask set having a plurality of reusable masks corresponding to a plurality of hard intellectual property (IP) components; a generic array type cell mask; and a custom blocking mask that includes blocking regions that positionally correspond with a set of IP components printed on a die.

REFERENCES:
patent: 5877632 (1999-03-01), Goetting et al.
patent: 6269467 (2001-07-01), Chang et al.
patent: 6383847 (2002-05-01), Ditlow et al.
patent: 6678645 (2004-01-01), Rajsuman et al.
patent: 6976197 (2005-12-01), Faust et al.
patent: 7176716 (2007-02-01), Madurawe

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