Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
Reexamination Certificate
2011-06-14
2011-06-14
Kim, Kenneth S (Department: 2111)
Electrical computers and digital processing systems: processing
Processing control
Processing control for data transfer
C712S219000, C712S029000, C712S029000
Reexamination Certificate
active
07962730
ABSTRACT:
In one embodiment, a processor comprises a retire unit and a load/store unit coupled thereto. The retire unit is configured to retire a first store memory operation responsive to the first store memory operation having been processed at least to a pipeline stage at which exceptions are reported for the first store memory operation. The load/store unit comprises a queue having a first entry assigned to the first store memory operation. The load/store unit is configured to retain the first store memory operation in the first entry subsequent to retirement of the first store memory operation if the first store memory operation is not complete. The queue may have multiple entries, and more than one store may be retained in the queue after being retired by the retire unit.
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Chang Po-Yung
Lien Wei-Han
Apple Inc.
Kim Kenneth S
Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
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