Semiconductor memory device having improved cell array layout

Details Semiconductor memory device having improved cell array layout Semiconductor memory device having improved cell array layout

1998-02-26

2000-05-16

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, G11C 800

Patent

active

060646187

ABSTRACT:
Each of first and second cell array groups has a cell array and a row decoder. Circuit blocks including a reset transistor, a Y selector, a write transistor, a block decoder, and a source decoder except the cell array and row decoder are arranged in the area between the first and second cell array groups. Since an address signal, a control signal, and a power supply common to the circuit blocks can be shared, the layout area can be reduced.

REFERENCES:
patent: 5659513 (1997-08-01), Hirose et al.
patent: 5838627 (1998-11-01), Tomishima et al.

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