Electrical computers and digital data processing systems: input/ – Interrupt processing – Interrupt prioritizing
Reexamination Certificate
2011-08-09
2011-08-09
Zaman, Faisal M (Department: 2111)
Electrical computers and digital data processing systems: input/
Interrupt processing
Interrupt prioritizing
C710S262000, C710S264000, C710S267000, C710S268000, C710S269000
Reexamination Certificate
active
07996595
ABSTRACT:
Technologies are generally described herein for handling interrupts within a multiprocessor computing system. Upon receiving an interrupt at the multiprocessor computing system, a priority level associated with an interrupt handler for the interrupt can be determined. Current task priority levels can be queried from one or more processors of the multiprocessor computing system. One of the processors can be assigned to execute the interrupt handler in response to the processor having a lowest current task priority level. Interrupt arbitration can schedule and communicate interrupt responses among processor cores in a multiprocessor computing system. Arbitration can query information about current task or thread priorities from a set of processor cores upon receiving an interrupt. The processor core that is currently idle or running the lowest priority task may be selected to service the interrupt.
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Hope Baldauff Hartman LLC
Lstar Technologies LLC
Zaman Faisal M
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