Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Optimization
Reexamination Certificate
2011-05-31
2011-05-31
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Optimization
Reexamination Certificate
active
07954079
ABSTRACT:
Provided is a method for compensating performance degradation of a radio frequency integrated circuit (RFIC) using an EM simulation. The method includes the steps of: (a) extracting the design specifications of the RFIC so as design and simulate a circuit; (b) designing the layout of the designed and simulated circuit, and extracting layout parameters by using the designed layout; (c) simplifying the layout and carrying out the EM simulation to extract performance parameters; (d) carrying out a circuit simulation by using the extracted layout parameters and performance parameters, and judging whether the results of the circuit simulation satisfy the design specifications of the RFIC or not; (e) when it is judged that the results of the circuit simulation satisfy the design specifications of the RFIC, performing a circuit manufacturing process; and (f) when it is not judged that the results of the circuit simulation satisfy the design specifications of the RFIC, partially removing the layout, and carrying out the EM simulation, thereby analyzing and compensating a performance degradation region.
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patent: 6557145 (2003-04-01), Boyle et al.
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Korean Intellectual Property Office, Notice of Allowance issued Jun. 25, 2008, (not translate yet).
Kim Hak Sun
Kim Yu Sin
Lee Chang Seok
Lee Kwang Du
Yang Chang Soo
Do Thuan
Lowe Hauptman & Ham & Berner, LLP
Samsung Electro-Mechanics Co. Ltd.
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