Methods for full gate silicidation of metal gate structures

Details Methods for full gate silicidation of metal gate structures Methods for full gate silicidation of metal gate structures

2011-01-04

2011-01-04

Landau, Matthew C (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S199000, C438S649000, C438S678000, C257SE21165

Reexamination Certificate

active

07863192

ABSTRACT:
One embodiment relates to a method of fabricating an integrated circuit. In the method, p-type polysilicon is provided over a semiconductor body, where the p-type polysilicon has a first depth as measured from a top surface of the p-type polysilicon. An n-type dopant is implanted into the p-type polysilicon to form a counter-doped layer at the top-surface of the p-type polysilicon, where the counter-doped layer has a second depth that is less than the first depth. A catalyst metal is provided that associates with the counter-doped layer to form a catalytic surface. A metal is deposited over the catalytic surface. A thermal process is performed that reacts the metal with the p-type polysilicon in the presence of the catalytic surface to form a metal silicide. Other methods and devices are also disclosed.

REFERENCES:
patent: 6730572 (2004-05-01), Lee et al.
patent: 6905622 (2005-06-01), Padhi et al.
patent: 2006/0258074 (2006-11-01), Visokay et al.
patent: 2007/0184652 (2007-08-01), Frank et al.

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