Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-08-16
2011-08-16
Elmore, Stephen (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S129000, C711S156000, C711S173000
Reexamination Certificate
active
08001330
ABSTRACT:
A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first directory to access the first array slice while using a second directory to access the second array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In one embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. The cache array is arranged with rows and columns of cache sectors wherein a cache line is spread across sectors in different rows and columns, with a portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency.
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Clark Leo James
Fields, Jr. James Stephen
Guthrie Guy Lynn
Starke William John
Elmore Stephen
Goldschmidt Craig
International Business Machines - Corporation
Musgrove Jack V.
Talpis Matthew B.
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