Dual node access storage cell having buffer circuits

Details Dual node access storage cell having buffer circuits Dual node access storage cell having buffer circuits

2011-07-19

2011-07-19

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S189050, C365S189070

Reexamination Certificate

active

07983071

ABSTRACT:
An integrated circuit includes an array of memory cells, each including a core storage element with first and second complementary storage nodes and first and second cell pass transistors coupled to the first and second storage nodes, respectively. In the cell, a first bitline (BL) is coupled to a first BL node in a source drain path of the first cell pass transistor, and a second BL is coupled to a second BL node in a source drain path of the second cell pass transistor. Each of the memory cells also includes a first buffer circuit comprising a first buffer pass transistor and a first driver transistor coupled to the source drain path of the first cell pass transistor, where the first buffer pass transistor is between the first BL node and the first driver transistor. The memory cells also include a second buffer circuit comprising a second buffer pass transistor and a second driver transistor coupled to a source drain path of the second cell pass transistor, where the second buffer pass transistor is between the second BL node and the second driver transistor. The gates of the first and second driver transistors are coupled to the second and first storage nodes, respectively. The cells include at least a first wordline coupled to the first and second cell pass transistors and the first and second buffer pass transistors.

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Ted Houston, U.S. Appl. No. 12/209,418, “Storage Cell Having Buffer Circuit for Driving the Bitline ,” filed Sep. 12, 2008.
Ted Houston et al., U.S. Appl. No. 12/209,456, “Memory Cell Layout Structure with Outer Bitline ,” filed Sep. 12, 2008.

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