Dynamic frequency adjustment for interoperability of...

Details Dynamic frequency adjustment for interoperability of... Dynamic frequency adjustment for interoperability of...

2011-06-21

2011-06-21

Suryawanshi, Suresh K (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C327S119000, C370S503000

Reexamination Certificate

active

07966510

ABSTRACT:
A system and method for dynamic frequency adjustment for interoperability of differential clock recovery, comprising: a frequency generator for receiving a frequency reference clock signal and generating a plurality of frequency signals, the plurality of frequency signals being output from the frequency generator and each having a different frequency; a flexible distributor for receiving the plurality of frequency signals from the frequency generator, and transmitting selected frequency signals; and a plurality of differential units, each for receiving the selected frequency signals, applying a differential signal to the selected frequency signals, adding time stamps to the selected frequency signals, and outputting respective time stamped differential selected frequency signals.

REFERENCES:
patent: 6380774 (2002-04-01), Saeki
patent: 6522207 (2003-02-01), Boerstler et al.
patent: 6762629 (2004-07-01), Tam et al.
patent: 6798790 (2004-09-01), Enssle et al.
patent: 6836169 (2004-12-01), Richmond et al.
patent: 7599458 (2009-10-01), Naffziger et al.

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