Error-correction memory architecture for testing production...

Details Error-correction memory architecture for testing production... Error-correction memory architecture for testing production...

2011-07-19

2011-07-19

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

07984358

ABSTRACT:
A system includes a first circuit generating error-correction (EC) bits based on test data. Memory comprises a plurality of memory lines each including a data portion storing the test data and an error-correction (EC) portion storing corresponding ones of the EC bits. An input receives the test data. A switching device selectively outputs one of the test data from the input and the EC bits and the test data from the first circuit to the memory. The test data comprise T pairs of test vectors. A first test vector of each of the T pairs of test vectors is an inverse of a second test vector of each of the T pairs of test vectors. Each of the first test vectors in the T pairs of test vectors is unique and each of the second test vectors in the T pairs of test vectors is unique. T is an integer greater than one.

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