Electrical test structure to detect stress induced defects...

Details Electrical test structure to detect stress induced defects... Electrical test structure to detect stress induced defects...

2011-06-28

2011-06-28

Tran, Minh-Loan T (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

C257SE21521, C438S017000

Reexamination Certificate

active

07968878

ABSTRACT:
A serpentine double gated diode array for monitoring stress induced defects is disclosed. The diode array is configured with adjacent gate segments and gate loops in close proximity to active areas to maximize a sensitivity to stress induced defects. The diode array is compatible with conventional electrical testing. Scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM) may be used to isolate individual stress induced defects. Variations in the gate configuration allow estimation of effects of circuit layout on formation of stress induced defects.

REFERENCES:
patent: 6762918 (2004-07-01), Voldman

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