Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-10-12
2001-11-06
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S593000, C438S647000
Reexamination Certificate
active
06313021
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to a device and process for the fabrication of sub-micron p-channel MOS (PMOS) devices and more specifically, to a process for forming a layered silicon gate that improves silicide integrity and substantially prevents boron penetration during a doping process.
BACKGROUND OF THE INVENTION
As is well known, transistors in semiconductor devices are commonly constructed on silicon wafers using a chemical vapor deposition (CVD) process along with many other process steps. Individual transistor components are fabricated on a wafer using conventional deposition and etching techniques. Components are formed over either n-tub or p-tub regions in the silicon substrate. The individual transistor regions are then doped with either an n-type or p-type dopant according to the desired type of semiconductor device.
In p-channel metal oxide semiconductor (PMOS) devices, boron is typically the p+dopant that is implanted into the source/drain regions. However, during this phase of the manufacturing step, heavily doped boron in the polysilicon gate has a tendency to diffuse laterally around the gate or transversely through the gate and into the p-channel areas of the device. This diffusion often leads to severe threshold voltage instablilities and reliability problems in the PMOS device.
To minimize the diffusion of these dopants, a barrier layer is typically formed over the polysilicon gate. In many instances, the barrier layer may comprise a tungsten nitride, a tungsten silicide nitride or a titanium-nitride (TiN). The titanium-nitride has problems associated with its use because it oxidizes at ambient temperatures making it prone to oxidation problems. Furthermore, titanium-nitride cannot withstand the high temperatures of certain subsequent processing steps, such as source/drain annealing, which typically occurs around 900° C. to 1000° C.; thus, it cannot be used in deposition schemes in which these temperatures are encountered. While tungsten-based silicides can withstand high temperature anneals, a problem arises with their use when they are used with conventional gate deposition process, as explained below.
As the size of gate devices has reached the sub-micron range (i.e., 0.25 microns or less), the integrity of the junction or interface between the polysilicon gate structure and the silicide barrier layer has become an issue. In conventional processes, polysilicon or amorphous silicon is typically used to form the gate structure, which is subsequently overlayed with a metal-based barrier layer, such as tungsten nitride or tungsten slicide nitride. This barrier layer/gate structure formation is typically followed by a high temperature anneal of some type. During this anneal, the silicide integrity at the junction/interface between the polysilicon gate and the silicide barrier layer becomes corrupt, which often leads to leakage, and thus, penetration of the boron dopant through the gate structure and into the p-channel. This problem is even more acute where the gate structure is initially formed from amorphous silicon.
As well known, amorphous silicon re-crystallizes into polysilicon in the presence of annealing temperatures in excess of 500° C. In such instances, re-crystallization can cause abnormal grain growth, which in turn, corrupts the silicide integrity and allows the dopant to penetrate into the p-channel.
Accordingly, what is needed in the art is a process that provides for a gate structure that can withstand annealing temperatures such that suppression of dopant penetration, both lateral and transverse, occurs with a simultaneous improvement of the silicide integrity.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a process for forming a sub-micron p-type metal oxide semiconductor (PMOS) structure on a semiconductor substrate. In one advantageous embodiment, the process includes forming a gate oxide on the semiconductor substrate, forming a gate layer on the gate oxide by depositing a first gate layer on the gate oxide at a first deposition rate and depositing a second gate layer on the first layer at a second deposition rate. Preferably, the gate is formed to a width of about 0.25 microns or less and to a thickness of about 100 nm. Of course, it is readily apparent that the present invention could also includes more than two layers. In fact, it is believed that overall structural integrity of the gate is further enhanced by adding additional layers with differing deposition rates. It is believed that the oscillation of the deposition rate provides an improved stress accommodation within the gate structure. The process further includes forming a silicide dopant barrier on the gate. Due to the presence of the improved stress accommodation in the gate, the integrity of the silicide dopant barrier is substantially enhanced. This increased silicide integrity prevents significant damage to the silicide dopant barrier layer during subsequent fabrication processes. As such, the dopant barrier is able to provide the intended degree of resistance to dopant penetration, for example boron, during the formation of source and drain regions adjacent the gate structure.
Thus, the present invention is directed to a process that provides suppression of dopant penetration, both lateral and transverse, with a simultaneous improvement of silicide integrity in PMOS gate structures.
In one embodiment, forming the dopant barrier includes forming a tungsten nitride barrier and in another embodiment, forming the dopant barrier includes forming a tungsten silicide nitride barrier.
In an particularly advantageous embodiment, forming a first gate layer includes forming the first gate layer at a first deposition rate ranging from about 1 nm to about 1.5 nm per minute and forming a second gate layer includes forming the second gate layer at a second deposition rate ranging from about 3 nm to about 5 nm per minute. It is believed that this perturbation in the deposition rate provides improved stress accommodation, which in turn enhances or improve the integrity of the silicide dopant barrier.
The structure may be formed by depositing first and second layers of polysilicon. In such embodiments, the first and second polysilicon layers are formed from a low pressure chemical vapor deposition of silane at a temperature of about 600° C. and at a pressure ranging from about 0.25 torr to about 0.5 torr. Again, it is believed that the perturbation formed by oscillating the deposition rate of the first and second layers provides a more uniform grain size, which provides the improved integrity of the silicide dopant barrier.
In an alternative embodiment, forming the first and second gate layers includes forming first and second gate layers from amorphous silicon. In this particular embodiment, the first and second amorphous layers are formed at a temperature less than about 550° C. at a pressure ranging from about 0.25 torr to about 0.5 torr and subjecting the first and second amorphous silicon layers to a temperature of about 600° C. to re-crystalize the amorphous silicon into a polysilicon have an enhanced uniform grain size and distribution. It is believed that this enhanced uniform grain size and distribution provides an improved silicide dopant barrier integrity.
In another embodiment, the process further includes subjecting the PMOS structure to a high temperature anneal having a temperature that ranges from about 900° C. to about 1000° C. This anneal is conducted subsequent to the formation of the silicide dopant barrier and is typically used to diffuse the boron dopant into the source and drain regions adjacent the gate. In yet another embodiment, the process may include forming an n-type metal oxide semiconductor (NMOS) structure adjacent the PMOS device.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention tha
Merchant Sailesh M.
Radosevich Joseph R.
Roy Pradip K.
Agere Systems Guardian Corp.
Lindsay Jr. Walter L.
Niebling John F.
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