Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2000-11-03
2001-11-27
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S080000, C326S027000
Reexamination Certificate
active
06323687
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to output drivers for integrated circuit chips, and more particularly to reducing the variation in the slew time of the output buffer.
BACKGROUND OF THE INVENTION
Many integrated circuit chips, particularly memory chips, are being manufactured with two power supply voltages: the standard VCC voltage for powering the core electronics of the chip, and a second voltage VCCQ for powering the output drivers (also called output buffers) of the chip. The output drivers convey the chip's output signals to other chips of the digital system in which the chip is placed, and draw a large amount of current and power to do so. The switching of the output drivers can generate relatively large current and voltage spikes on the power supply and return lines. For this reason, output drivers are typically designed to have controlled rise and fall slew times so that they do not switch logic states too quickly. Because the magnitudes of the current and voltage spikes are proportional to the slew times, controlling the slew times will control the magnitudes of the spikes.
Using a separate supply voltage VCCQ for the output drivers has at least two advantages. First it enables one to use different external bypass capacitors for the two supplies VCC and VCCQ, which helps to isolate the current and voltage spikes from the core of the integrated circuit. Second, it enables one to adjust the output voltage levels of the chip to match those of the digital system without the use of special interface circuitry. As in known in the art, the electronics industry is using a wide variety of supply voltages for digital circuits, ranging from 1.5 V to 5 V, with 2.5V and 3.3 V being popular choices. Memory devices are used in a wide variety of applications, which are powered by a wide range of voltages. Often it is found that the speed performance of a memory device works well at a particular voltage, which may or may not be the same as the voltage used by the rest of the digital system. The second VCCQ supply enables the circuit designer to provide the core of the memory device with the voltage that optimizes its performance through the VCC pin, and to provide the output drivers with the voltage that interfaces with the rest of the digital system through the VCCQ pin.
However, part of the overall speed performance of a memory device (or other digital circuit chip) is dependent upon both the speed performance of the chip's core circuits and the rising and falling slew times of the output drivers. In current chip designs, these slew times are highly dependent upon the value of the VCCQ voltage. And thus, a circuit designer is constrained to a limited range of VCCQ if he wants to achieve optimal speed performance from the chip.
SUMMARY OF THE INVENTION
The present invention recognizes that the rise and fall times at the output node of an output driver can also be made to depend upon the rate at which the gate of driver's pull-down transistor is discharged (for rising transitions at the output node), and upon the rate at which the gate of driver's pull-up transistor is charged (for falling transitions at the output node). The present invention further recognizes that the charging and discharging of the gates of pull-up and pull-down can be controlled to compensate for the variation in slew times due to variations in VCCQ and to thereby reduce this variation caused by different values of VCCQ.
Broadly stated, the present invention encompasses an output buffer for a digital integrated circuit chip, the chip having a core which is powered by a first supply voltage VCC which is received at a first supply voltage port. Broadly stated, an output buffer according to the present invention comprises a second supply voltage port for receiving a second supply voltage VCCQ, a power return line port, an output port for providing a voltage output, and an input port for receiving an input data value representative of the voltage value to be provided at said output. The input data value has a first state when a logic-low voltage is to be generated at the output and a second state when a logic-high voltage is to be generated at the output. The output buffer further comprises a pull-up transistor having a gate electrode, a source electrode, and a drain electrode, one of the source and drain electrodes being coupled to the second voltage supply port and the other of said source and drain electrodes being coupled to the output, and a pull-down transistor having a gate electrode, a source electrode, and a drain electrode, one of the source and drain electrodes being coupled to the return line port and the other of said source and drain electrodes being coupled to the output. The output buffer further comprises one or both of a first logic control circuit and a second logic control circuit, and comprises both in preferred embodiments.
The first logic control circuit is responsive to the input data value and the value of second supply voltage VCCQ, and discharges the gate of the pull-up transistor when the input data value is in its second state. The first logic control circuit discharges the gate of the pull-up transistor at a rate which varies with the value of the second supply voltage. The second logic control circuit is responsive to the input data value and the value of second supply voltage VCCQ, and charges the gate of the pull-down transistor when the input data value is in its second state. The second logic control circuit discharges the gate of the pull-down transistor at a rate which varies with the value of the second supply voltage.
According, it is an object of the present inventions to control the slew times of an output driver predictable amounts over a wide variation in VCCQ.
It is another object of the present inventions to provide output drivers which can be used in a wide variety of circuit applications while maintaining a low noise characteristic of the power supply and return lines, and maintaining low cross-talk on adjacent electrical lines.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention, the accompanying drawings, and the appended claims.
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Coudert Brothers
Fujitsu Limited
Le Don Phu
Tokar Michael
LandOfFree
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