Method and apparatus for moving data between storage levels...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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Details

C711S004000, C711S165000, C711S112000, C711S209000, C711S118000, C711S122000, C711S171000, C711S161000

Reexamination Certificate

active

06311252

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates generally to hierarchical data storage systems and more particularly to data storage management in such systems.
Data storage systems are available for use by host processors to store the increasingly large amounts of data that are being generated, accessed, and or analyzed by applications running on those host processors. Today the capacity of such data storage systems is measured in terra bytes.
A typical data storage system might include three levels of data storage, namely, a cache memory, an array of disks, and a tertiary storage device, such as a tape drive or a farm of tape drives, that can be connected to the system through an appropriate interface. The cache memory, which may be implemented by high speed RAM (Random Access Memory), provides storage for data that is being accessed by the applications running on the host processors. It is the working memory. The array of disks, which provides much larger storage capacity than the cache memory and might include hundreds of disk devices, provides the more permanent storage for the data. The disks are not practical for use as the working memory because they are much slower than the cache memories. Data is staged from the array of disks (i.e., the slower storage) to cache memory (the faster storage) when it is needed by the host processors and it is destaged back from cache memory to the array of disks when it is not needed.
The tertiary storage provides the most permanent storage for the data. Since the tape drives that are often used for the tertiary storage are much slower than the disk devices, the tertiary storage is only used for data that is accessed very infrequently.
Known techniques are available for moving data from tertiary storage to cache storage and for determining what data should be moved to tertiary storage. Typically, the decision on what data should be destaged is based on some measure of access frequency. In general, the systems which include such multiple levels of storage are referred to as hierarchical data storage systems and the techniques for managing the data flow between the levels are referred to generally as hierarchical storage management.
SUMMARY OF THE INVENTION
In general, the invention is a hierarchical storage management system which uses a constrained mapping scheme.
In one aspect, the invention is a method of moving data between first, second, and third storage levels of a hierarchically arranged data storage system. The method includes dividing address space into a plurality of contiguous segments, each of which is further divided into a plurality of contiguous groups. Each of the groups may store a sequence of records, each of which is represented by a sequence of bytes. When it is necessary to move a designated record between the second and third levels of data storage, the segment in which that designated record is stored is moved; and when it is necessary to move the designated record between the first and second levels, the group in which that designated record is stored is moved.
Preferred embodiments include the following features. The data storage system includes cache memory, disk arrays, and tape drives, and the method further includes the steps of: implementing the first level of data storage in the cache memory; implementing the second level of storage in the disk arrays; and implementing the third level of storage in the tape drives.
In general, in another aspect, the invention includes the steps of dividing address space in the manner described above and then constraining data movement between the first and second levels to be in blocks made up of one or more groups; and constraining data movement between the second and third levels to be in blocks made up of one or more segments.
In general, in still another aspect, the invention includes the steps of dividing address space in the manner described above and then moving data between the second and third levels only in blocks that are made up of one or more segments; and moving data between the first and second levels only in blocks that are made up of one or more groups.
In preferred embodiments, the step of moving data between the second and third levels involves moving data only in blocks that are made up of one segment, and the step of moving data between the first and second levels involves moving data only in blocks that are made up of one group.
In general, in yet still another aspect, the invention is directed to a hierarchical data storage system for use by one or more host processors to store data. The system includes: one or more interfaces by which the one or more host processors are connected to the data storage system; an internal bus; a cache memory, an array of disks, and a controller connected to the bus; and an interface for connecting a tertiary storage devices to the storage system. The into a plurality of contiguous groups, wherein each of the groups is for storing a sequence of records. The controller is programmed to perform the following functions: when it is necessary to move a designated record between the tertiary storage device and the array of disks, the controller moves the segment in which that designated record is stored; and when it is necessary to move the designated record between the cache memory and the array of disks, the controller moves the group in which that designated record is stored.
The addressing approach used in the invention allows for very compact indexes and this in turn allows for quick access rates. It produces a substantial decrease in the size of the index that is required and it preserves order among the data that is stored in the system.
Other advantages and features will become apparent from the following description of the preferred embodiment and from the claims.


REFERENCES:
patent: 5206939 (1993-04-01), Yanai et al.
patent: 5737747 (1998-04-01), Vishlitzky et al.
patent: 5778394 (1998-07-01), Galtzur et al.
patent: 5802557 (1998-09-01), Vishlitzky et al.
patent: 5809435 (1998-09-01), Yeger et al.

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