Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral adapting
Reexamination Certificate
1999-02-09
2001-11-27
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral adapting
C710S016000, C710S065000, C332S100000, C332S101000
Reexamination Certificate
active
06324603
ABSTRACT:
TECHNICAL FIELD
The present invention relates to interface technology for providing mutual connection between data processing devices, which conduct data processing, and peripheral devices, which conduct input/output of information, and the like, and more particularly, it relates to a new interface technology standard relating to connections between game devices and related peripheral devices.
BACKGROUND ART
Data transmission methods for use in data communications between the main unit of an image processing device and peripheral devices related thereto include the following.
Philips, I
2
C Bus System
In this system, serial data and a serial clock are transmitted by two wires. The data and clock are physically separated, and data transmission/reception and reproduction are possible by the simplest method. The I
2
C bus is described, for example, in Philips' I
2
C bus instruction manual (January 1992).
SGS—Thomson DS Link System
In this system, a data signal and strobe signals are transmitted by two wires. A clock signal is reproduced by means of the data signal and strobe signal. When the transmitted data changes to a different value, only the data signal changes. When the transmitted data is the same value, only the strobe signal changes. For example, if the transmitted data in the data signal changes from “0”→“1”, or “1”→“0” then the strobe signal does not change. If the transmitted data in the data signal does not change, e.g., “0”→“0”, or “1”→“1”, then the strobe signal only changes. Therefore, by adopting an exclusive-OR operation for the data signal and strobe signal, it is possible to reproduce a clock signal. The DS link system is introduced in
Nikkei Electronics
, Vol. 675, (Nov. 4
th
, 1996, pp. 167-171). In consumer-oriented devices, such as game devices, it is necessary to use a data transmission system and interface connection standard which can be implemented at low cost. However, in the aforementioned I
2
BUS system, since the transition edge of the data signal has the same timing as the transition edge of the clock, it is not possible to use the clock signal directly on the data reproducing (demodulating) side. Furthermore, in the latter DS link system, exclusive-OR logic is applied to the data signal and strobe signal, to reproduce a synchronizing clock. The data signal must be sampled using this clock. Therefore, the level of simplicity of the interface circuit structure does not adequately satisfy the conditions for domestic game devices, where low cost is a very important requirement.
Consequently, it is an object of the present invention to provide a data transmission system for an interface having an inexpensive circuit composition, which can be applied to an image processing device, such as a domestic game system. It is a further object of the present invention to provide a data transmission system for an interface, whereby data can be separated from a signal carrying data by means of a simple circuit composition.
It is a further object of the present invention to provide a game device and a related peripheral device comprising interfaces, whereby data can be separated from a signal carrying data by means of a simple circuit composition.
It is a further object of the present invention to provide basic technology for developing various types of peripheral devices, by proposing novel interface technology between a game device and peripheral device.
DISCLOSURE OF THE INVENTION
In order to achieve the aforementioned objects, the data transmission system according to the present invention is a data transmission system for transmitting data by distributing one item of serial data into first and second data signals, wherein the first data signal contains each of the odd-numbered bits of the serial data, respectively distributed between pulses of a first clock formed by means of a pulse sequence having a uniform interval; the second data signal contains each of the even-numbered bits of the serial data, respectively distributed between pulses of a second clock formed by means of a pulse sequence having the same frequency as the first clock signal; the first data signal is transmitted such that the pulse edge of its clock signal component is located in the data section of the second data signal on the time axis; and the second data signal is transmitted such that the pulse edge of its clock signal component is located in the data section of the first data signal on the time axis (
FIG. 10
,
FIG. 11
,
FIG. 50
, FIG.
54
). Furthermore, in a data transmission system wherein a data frame defined according to a transmission format comprising, at the least, a start pattern carrying data start information, a data pattern carrying serial data, and an end pattern carrying data end information, are transmitted by distributing the data frame between a first and a second data signal, the data transmission system according to the present invention is a data transmission system; wherein the start pattern is created by setting the first data signal to a constant value and setting the second data signal as a first pulse sequence signal; the data pattern is created by forming the first data signal by distributing each of the odd-numbered bits of the serial data respectively between pulses of a second pulse sequence signal having a constant interval, and forming the second data signal by distributing each of the even-numbered bits of the serial data respectively between pulses of a third pulse sequence signal, which is shifted by a prescribed amount from the position on the time-axis of the second pulse sequence signal; and the end pattern is created by setting the second data signal to a constant value, and setting the first data signal as a fourth pulse sequence signal. (
FIG. 11
,
FIG. 12
,
FIG. 50
,
FIG. 54
)
By means of this composition, it is possible to create a communications interface wherein the modulation and demodulation circuits can be composed relatively simply by means of a small number of data lines (namely, two data lines).
Preferably, the superimposed data is isolated by latching the level of one data signal of the first and second data signals at the pulse edge of the clock signal component of the other data signal. Thereby, it is possible to isolate the superimposed data by means of a simple circuit composition (
FIG. 10
,
FIG. 28
,
FIG. 29
, FIG.
50
).
In a game device which requests transmission or reply of information required for a game by transmitting two data signals (SDCKA, SDCKB) simultaneously to a single or plurality of peripheral devices by means of a signal transmission path, the game device according to the present invention comprises: start pattern creating means for creating a start pattern represented by two data signals, wherein a first data signal is set to a constant value (or fixed value) state during a first time period, and a second data signal is set to a clock signal state during the first time period (FIG.
13
(
a
),
FIGS. 14
,
58
,
204
c
); data pattern creating means for creating a data pattern represented by two data signals, wherein data to be transmitted to the peripheral device is divided into two data sequences, and a first data signal is created by inserting each bit of the first data sequence respectively between pulses of a first clock signal, and a second data signal is created by inserting each bit of the second data sequence respectively between pulses of a second clock signal having the same frequency as, and a prescribed phase difference from, the first clock signal (
FIGS. 10
,
204
e
); end pattern creating means for creating an end pattern represented by two data signals, wherein the second signal is set to a constant value (or fixed value) state during a second time period, and the first signal is set to a clock signal state during the second time period (
FIGS. 13
,
58
,
204
c
); and frame creating means for creating a frame represented by two data signals, containing the start pattern, the data pattern and the end pattern, and transmitting the frame as a transmission unit to
Himoto Atsunori
Niizuma Naoki
Kabushiki Kaisha Sega Enterprises
Keating & Bennett LLP
Lee Thomas
Peyton Tammara
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