Low leakage circuit configuration for MOSFET circuits

Details Low leakage circuit configuration for MOSFET circuits Low leakage circuit configuration for MOSFET circuits

1998-07-08

2000-05-16

Santamauro, Jon

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

326 34, 326 83, H03K 1716

Patent

active

060642238

ABSTRACT:
A circuit configured with MOSFETs having a first range of subthreshold conduction, is provided with at least one switchable pathway between the circuit and a power or ground node, such that the switchable pathway is operable to substantially reduce leakage current through the circuit. In a further aspect of the present invention, the switchable pathway is a FET having substantially the same subthreshold conduction characteristics as the FETs in the circuit to which the switchable pathway is coupled, the FET being configured to be driven into both inversion and accumulation.

REFERENCES:
patent: 5043604 (1991-08-01), Komaki
patent: 5594371 (1997-01-01), Dousaki
patent: 5801548 (1998-09-01), Lee et al.
patent: 5864506 (1999-01-01), Arcoleo et al.
patent: 5949254 (1999-09-01), Keeth

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