Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2000-10-11
2001-11-20
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S185200, C365S185210, C365S185250
Reexamination Certificate
active
06320808
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a memory read amplifier circuit with high current level discrimination capacity. More particularly, the memory device is a EEPROM capable of discriminating very low current levels yet maintaining good read speed characteristics.
BACKGROUND OF THE INVENTION
In memory devices, such as EEPROMS, a unit of information is stored in a floating-gate transistor. Depending on the logic state to be stored (i.e., a logic 0 or a logic 1), a positive or negative electrical charge is trapped in the floating gate of the transistor, thus altering its threshold. If no electrical charges are stored in the floating gate, the memory cell is termed virgin, otherwise it is deleted or written.
The correspondence between the deleted or written logic states depends on conventions which can change from product to product. The logic state of the cell is recognized on the basis of the current that flows across it in very specific bias conditions. If a negative charge is trapped in the floating gate of the transistor, the threshold of the cell is higher than in a virgin cell. Otherwise, the threshold is lower than in a virgin cell.
In most cases, the information is obtained from a comparison between the current of the cell and the current of an appropriate reference, which can be absolute (a constant current) or derived from a virgin cell which is biased in exactly the same manner as the cell whose state is to be sensed. In conventional read amplifier circuits this comparison is performed by using current/voltage (I/V) converters. These converters are formed by current mirrors using P-channel transistors.
Read amplifier circuits are therefore often based on a current mirror between two branches, as shown in FIG.
1
. This figure shows how the drain terminals of the reference memory cells
1
and
2
are connected to a bit line and a decoder selects one of them. One circuit is connected to the bit line of the selected cell and at the same time a similar circuit is connected to the virgin cell located external the cell array, or to the reference memory cells depending on the situation.
The resulting two different currents are usually mirrored on PMOS transistors and are converted into voltages by a current/voltage converter which is formed using PMOS transistors. The resulting voltages, designated in
FIG. 1
by Vref and Vcell, are applied to the inputs of a differential comparator
3
. The differential comparator
3
compares the two voltages and provides at an output a logic value related to the state of the memory cell being considered.
The approach shown in
FIG. 1
can have limitations when the supply voltage Vdd drops to approximately 1.8 V due to the presence of the diode-connected PMOS transistor. The speed of the read amplifier circuit of
FIG. 1
is further greatly influenced by the reference current. When the reference current tends to become very low the amplifier circuit accordingly tends to become very slow.
Therefore, a drawback of conventional read amplifier circuits is that they are unable to discriminate very low currents while maintaining good speed and functionality characteristics even at supply voltages below 2 V. Moreover, conventional read amplifier circuits are unable to operate over a wide range of supply voltages. This characteristic would be highly desirable for applications in so-called smart cards, for example.
SUMMARY OF THE INVENTION
In view of the foregoing background, an object of the present invention is to provide a memory read amplifier circuit that discriminates very low current levels while maintaining good performance in terms of speed.
Another object of the present invention is to provide a memory read amplifier circuit that operates over a wide range of supply voltages.
Yet another object of the present invention is to provide a memory read amplifier circuit that ensures biasing of the controlled bit lines in a variety of temperature and supply conditions.
Another object of the present invention is to provide a memory read amplifier circuit having good noise rejection.
A further object of the present invention is to provide a memory read amplifier circuit having a differential comparator with very fast output switching times.
Yet a further object of the present invention is to provide a memory read amplifier circuit that is highly reliable, relatively easy to manufacture and at competitive costs.
These objects, advantages and features which will become more apparent hereinafter are achieved by a memory read amplifier circuit comprising a first pre-charge amplifier circuit connected to a bit line which is connected to a memory cell to be read, and a second pre-charge amplifier circuit connected to a reference bit line which is connected to a reference memory cell.
The memory read amplifier circuit further includes a differential comparator which compares a first voltage signal and a second voltage signal obtained from respective current signals related to the memory cell to be read and to the reference memory cell. The first and second pre-charge amplifier circuits are respectively connected to the gate terminal of a first cascode circuit and of a second cascode circuit, which are in turn connected between a supply voltage and the memory cell to be read and the reference memory cell.
The gate terminals of the first and second cascode circuits are connected to inputs of the differential comparator. The gate voltage of the first and second cascode circuits are a function of the current signals of the memory cell to be read and of the reference memory cell, respectively.
REFERENCES:
patent: 5563826 (1996-10-01), Pascucci et al.
patent: 6191979 (2001-02-01), Uekubo
patent: 6205068 (2001-03-01), Yoom
patent: 405152874A (1993-06-01), None
Conte Antonino
Gaibotti Maurizio
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Galanthay Theodore E.
Lam David
Nelms David
STMicroelectronics S.r.l.
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