Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-07-15
2001-11-06
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S774000, C257S298000, C257S300000, C257S311000, C257S303000, C361S321400, C361S322000, C361S149000
Reexamination Certificate
active
06313491
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory and a method of fabricating the same and, more particularly, to a ferroelectric random access memory (to be referred to as an FRAM hereinafter) and a method of fabricating the same.
FRAM products or FRAM hybrid logic products have a cell circuit configuration as shown in FIG.
4
. Each cell has one transistor Tr and one capacitor C. One of source and drain diffusion layers of the transistor Tr is connected to one end of the capacitor C. The other one of the source and drain diffusion layers of the transistor Tr is connected to a bit line BL. The gate of the transistor Tr is connected to a word line WL. The other end of the capacitor C is connected to a plate line PL.
FIG. 3
shows the cell structure of this FRAM, which is pertinent to the present invention. The surface of a semiconductor substrate
71
is divided into a cell region and a peripheral circuit region. A drain diffusion layer
73
and a source diffusion layer
74
are formed in the cell region. A drain diffusion layer
76
and a source diffusion layer
77
are formed in the peripheral circuit region. Gate electrodes
72
and
75
are formed on the semiconductor substrate
71
via a gate oxide film. A BPSG film
78
is formed on these gate electrodes
72
and
75
to planarize their surfaces. On the surface of this BPSG film
78
, a silicon nitride film
79
and a silicon oxide film
80
as barrier layers are formed.
On the surface of the silicon oxide film
80
, a lower electrode
81
, a dielectric film
82
, and an upper electrode
83
are formed in this order to construct an FRAM capacitor. An insulating film
84
made from TEOS or the like is formed on the surfaces of this capacitor and a silicon oxide film
80
to planarize these surfaces.
The gate electrode
72
of the transistor Tr in the cell region is connected to the word line WL (not shown) formed on the insulating film
84
via a contact hole filled with a refractory metal such as titanium or tungsten. The drain diffusion layer
73
is connected to the bit line BL (not shown) formed on the insulating film
84
via a contact hole similarly filled with a refractory metal. The source diffusion layer
74
is connected to the upper electrode
83
of the capacitor via a refractory metal film filling a contact hole
85
and a first interconnecting layer
88
. The lower electrode
81
is connected to the plate line PL (not shown).
Contact holes are formed in the BPSG film
78
, the silicon nitride film
79
, the silicon oxide film
80
, and the insulating layer
84
to expose the surfaces of the source diffusion layers
74
and
77
. A refractory metal film
85
such as titanium or tungsten fills these contact holes. Also, a contact hole is formed in the insulating layer
84
to expose the surface of the upper electrode
83
. A refractory metal film
87
is formed on the inner surfaces of this contact hole.
The first interconnecting layer
88
made of aluminum or the like is formed on the surface of the insulating layer
84
and connected to the upper electrode
83
. This interconnecting layer
88
is also connected to the source diffusion layers
74
and
77
via the refractory metal films
85
and
87
filling the contact holes
85
.
An insulating film
89
is formed on the surfaces of the interconnecting layer
88
and the insulating layer
84
to planarize these surfaces. A second interconnecting layer
92
is formed on the surface of this insulating film
89
. The first and second interconnecting layers
88
and
92
are connected via contact holes
91
. A passivation film
93
covers the surfaces of the interconnecting layer
92
and the insulating layer
89
.
However, a semiconductor memory with the above structure has the following problem. As shown in
FIG. 3
, the contact hole for connecting the first interconnecting layer
88
to the source diffusion layer
74
on the surface of the semiconductor substrate
71
must be so formed as to have a depth equivalent to the total film thickness of the BPSG film
78
, the silicon nitride film
79
, the silicon oxide film
80
, and the insulating layer
84
. Therefore, the aspect ratio of the depth to the opening diameter of the contact hole increases to make the contact hole difficult to process and fill.
If the surface of the insulating layer
84
covering the FRAM capacitor is not planarized, the film thickness of this insulating layer
84
can be decreased, so the depth of the contact hole can also be decreased. In this case, however, the first interconnecting layer
88
formed on the insulating layer
84
is not planarized. This makes lithography and etching for pattering the interconnecting layer
88
difficult to perform.
As described above, the memory shown in
FIG. 3
has the problem that when an interconnecting layer is planarized, a contact hole connecting this interconnecting layer to the surface of a semiconductor substrate is deepened and made difficult to process and fill, so no micropatterning can be realized.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory which facilitates processing an interconnecting layer and processing and filling a contact hole connecting this interconnecting layer to a semiconductor substrate and can realize micropatterning, and a method of fabricating the same.
According to the present invention, there is provided a semiconductor memory having a cell including a transistor and a ferroelectric capacitor, comprising the ferroelectric capacitor formed on a surface of a semiconductor substrate via a first insulating layer, a first interconnecting layer formed on a surface of a second insulating layer so formed as to cover the ferroelectric capacitor, and a second interconnecting layer formed on a surface of a third insulating layer so formed as to cover the first interconnecting layer, and directly connected to an upper electrode of the ferroelectric capacitor via a contact hole formed in the second and third insulating layers.
In this semiconductor memory, the first interconnecting layer is formed below the second interconnecting layer directly connected to the upper electrode of the ferroelectric capacitor. This facilitates processing and planarizing the first interconnecting layer as the lower layer.
A third interconnecting layer may be formed inside the first insulating layer.
Also, the upper electrode of the capacitor and a diffusion layer of the transistor may be connected via the third interconnecting layer.
In this semiconductor memory, the first interconnecting layer is formed after the formation of the ferroelectric capacitor. This eliminates the problem that, e.g., the interconnecting material is melted by annealing in the ferroelectric capacitor formation step. Therefore, it is unnecessary to use a refractory metal as the interconnecting material and possible to use a low-resistance material, such as aluminum, as the interconnection. Also, the first contact hole can be easily processed and filled, and this contributes to micropatterning.
Furthermore, at least one of the first and second interconnecting layers may be made of a material containing at least one of aluminum and copper.
This semiconductor memory achieves micropatterning because the first contact hole can be easily processed and filled and the first interconnecting layer and the ferroelectric capacitor can be so formed as to vertically overlap each other via the insulating film.
The semiconductor memory fabrication method of the present invention is a method of fabricating a semiconductor memory having a cell including a transistor and a ferroelectric capacitor, comprising the steps of forming a first insulating layer on a surface of a semiconductor substrate, forming a ferroelectric capacitor on the first insulating layer, forming a second insulating film to cover the ferroelectric capacitor, forming a first interconnecting layer on the second insulating film, forming a third insulating film on the first interconnecting layer, forming a contact hole in the third and
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Williams Alexander O.
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