Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2000-02-04
2001-11-27
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S296000
Reexamination Certificate
active
06323112
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89100041, filed Jan. 4, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of fabricating integrated circuits (IC). More particularly, the present invention relates to a method of fabricating a metal-oxide-semiconductor (MOS) device.
2. Description of Related Art
The conventional method of fabricating the MOS device is to form a gate oxide layer and a polysilicon gate on the substrate. The polysilicon gate is used as the implantation mask, while dopants are implanted in the substrate by ion implantation to form the source/drain extension. After spacers are formed on sidewalls of the polysilicon gate, dopants are ion-implanted in the substrate to form the source/drain while using the polysilicon gate and spacers as the implantation mask. Afterwards, a high temperature annealing process is used to activate dopants in the source/drain extension and the source/drain. Lastly, a dielectric layer is formed over the substrate for further metal interconnects process.
In order to be compatible with the market requirement for the minimum device size, the semiconductor devices are manufactured with high integration at the present. The conventional method for increasing gate capacitance of the MOS device is to decrease the thickness of the gate oxide layer. However, it is not possible to keep decreasing the thickness of the gate oxide layer, especially when IC manufacture is moving into the sub micron processes. When the thickness of the oxide layer decreases to a certain level, the defects in the oxide layer cause current leakage of the device and reduction of drain current, and may even lead to severe short channel effect.
On the other hand, polysilicon or polycide material is used to form the gate layer in the conventional MOS device. In general, dopants are implanted in the polysilicon to increase its conductivity and reduce its resistivity. However, the dopant concentration is pretty limited in the polysilicon, which causes restricted resistivity reduction and further influences the speed as well as operation performance. Moreover, a depletion region is formed during the operation and a depletion capacitor is induced in this MOS device made of polysilicon or polycide material, causing capacitance of the whole transistor to decrease.
In addition, the boron atoms implanted during the ion implantation process of the source/drain extension and the source/drain might inject along the polysilicon lattice and penetrate the gate oxide layer. This raises problems in the electrical properties of the device. Furthermore, the high temperature armealing process performed after the ion implantation process of the source/drain extension and the source/drain causes changes in the implantation profile and results in a deeper junction depth than desired.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a MOS device, which can provide enough gate capacitance and prevent current leakage in the gate dielectric layer.
The invention provides a method of fabricating a MOS device, which method leaves a definite thickness of the gate dielectric layer to prevent poor reliability resulting from the gate dielectric layer being too thin as in the prior art, and provides enough gate current.
The invention provides a method of fabricating a MOS device, which method can prevent boron atoms from penetrating the gate made of polysilicon material, as in the prior art, and prevent the problems that would arise from the capacitance depletion region.
The invention provides a method of fabricating a MOS device, which method can reduce gate resistivity to enhance the operation performance of the device.
The invention provides a method of fabricating a MOS device, which method provides the source/drain extension with a shallow junction depth and maintains the implantation profile.
According to the purpose of the invention, a method of fabricating a MOS device is provided herein. An oxide layer is formed on a substrate; and a patterned dummy gate layer and a patterned cap layer are formed sequentially on the oxide layer. After reducing the width of the patterned dummy gate layer, the patterned cap layer serving as an implantation mask is used in a first ion implantation step to form a source/drain in the substrate. After removing the patterned cap layer, the narrower patterned dummy gate layer is used as an implantation mask for a second ion implantation step to form a source/drain extension in the substrate. Afterwards, a planarized dielectric layer is formed on the substrate and the top of the dummy gate layer is exposed. The dummy gate layer and its underlying oxide layer are removed to form an opening, which exposes the surface of the substrate, in the dielectric layer. A gate dielectric layer is formed on the bottom and sidewalls of the opening, and a metal gate is formed subsequently inside the remaining space of the opening.
According to the purpose of the invention, another method of fabricating a MOS device is provided herein. An oxide layer and a patterned dummy gate layer are formed on the surface of a substrate. The patterned dummy gate layer serving as an implantation mask is then used in a first ion implantation step to form a source/drain in the substrate. After performing a step to reduce the width of the patterned dummy gate layer, the narrower patterned dummy gate layer is used as an implantation mask for a second ion implantation step to form a source/drain extension in the substrate. Afterwards, a planarized dielectric layer is formed on the substrate. The dummy gate layer and its underlying oxide layer are then removed to form an opening, which exposes the surface of the substrate, in the dielectric layer. A gate dielectric layer is formed on the bottom and sidewalls of the opening, and a metal gate is formed subsequently inside the remaining space of the opening.
As embodied and broadly described herein, the patterned dummy gate layer is used as the implantation mask to form the source/drain. Then the width of the patterned dummy gate layer is reduced by a chemical dry etching process. The narrower patterned dummy gate layer is used as the implantation mask to form the source/drain extension. A high temperature annealing process is performed after the first ion implantation step of the source/drain, while a low temperature annealing process is performed after the second ion implantation step of the source/drain extension. The high temperature annealing process applied after the first ion implantation process of the source/drain is performed before the second ion implantation process of the source/drain extension. Additionally, the low temperature annealing process activates the source/drain extension formation with the expected profile and junction depth. Therefore, this invention can prevent the problems present in the prior art. In the prior art, the ion implantation process of the source/drain extension is applied before the high temperature annealing process, which causes problems derived from improper control of the implantation profile and the overly deep junction depth of the source/drain extension.
In contrast, the method of this invention forms the source/drain in the substrate before the metal gate. Because the high temperature annealing process of the source/drain is applied before the deposition process of the metal layer of the metal gate, the metal gate is free from damage of the high temperature annealing process.
In this invention, metal material is used for the gate as a substitute for the polysilicon or polycide material used in the prior art; therefore, the gate resistivity can be reduced to enhance the operation performance of the device. This invention prevents problems derived from the capacitance depletion region and boron penetration present is in the prior art.
In this invention, a dielectric layer with high dielectric constant is used to form the gate dielectric layer; hence the capacitance of t
Huang Jiawei
J.C. Patents
Nelms David
Taiwan Semiconductor Manufacturing Co. Ltd.
Vu David
LandOfFree
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