Semiconductor device

Details Semiconductor device Semiconductor device

2000-08-07

2001-11-20

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230030

Reexamination Certificate

active

06320814

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device comprising a memory having X rows or columns, where X is between Nth power of 2 and (N−1)th power of 2, and N is a natural number. In the following, this type memory is called an intermediate word size memory. More particularly, the present invention relates to a semiconductor device equipped with a memory for an intermediate word size that puts out “H (High)” or “L (Low)” as stored data when a row or column having a number larger than X is accessed.
Recently, semiconductor devices equipped with both logic circuits and memories have been used widely for special purposes.
FIG. 1
illustrates a block diagram of a semiconductor device equipped with both a logic circuit and memory. A semiconductor device
1
is equipped with a logic circuit
2
, a memory
3
accessed by the logic circuit
2
, and an input/output circuit
4
.
A semiconductor device such as shown in
FIG. 1
is usually designed based on the basic circuit configuration developed in advance, and it is modified according to its purpose. Since the required maximum memory capacity is decided depending on the purpose, a memory that will satisfy this requirement is provided accordingly. This decreases the area of the chip used in a semiconductor device, and power dissipation as well. In some cases, a memory to be installed is not replaced, instead only the necessary capacity of the memory is activated according to the required maximum memory. In this case, the area of the chip is not reduced but unwanted power dissipation will be saved.
The size of an address space that can be accessed by N-bit address signals is the Nth power of 2. Typically, a memory has an address space size of Nth power of 2 according to the bit number N of input address signals. This means that there is a memory location corresponding to every address addressed by an address signal. In a semiconductor device, whose memory size can be decided depending on its purpose, the size of a memory address space to be provided or activated may not be equal to the Nth power of 2. For example, a basic memory that can be accessed by 16-bit address signals has a 64 Kbyte address space, and if the maximum space actually used in application is 36 Kbyte, the area and power dissipation of the chip can be reduced by eliminating the part of the memory that corresponds to unused memory space of 28 Kbyte. In this case, this memory is called a memory for an intermediate word size.
However, address signals accessing the deleted addresses may be issued because the address signals are 16-bits. Therefore, the memory for an intermediated word size is designed so as to produce output “H” or “L” as data when such address signals are issued. A semiconductor device having a configuration shown in
FIG. 1
, is naturally designed to prevent an unequipped or inactivated address space in memory
3
from being accessed by logic circuit
2
, and if such invalid accesses, due to a malfunction, occur, they can be detected by an output “H” or “L”. Particularly in the performance test during manufacturing process of semiconductor devices such as mentioned above, the same test program is apt to be used for lower cost. In this case, address signals are applied regardless of the size of memory and when such an inexistent address space is accessed constantly, it can be detected by successive outputs “H” or “L”. Therefore, it is necessary to design the semiconductor device so that it produces output “H” or “L” as data when such a non-existent address space is accessed.
FIG. 2
illustrates an example of a memory for an intermediate word size configuration. Typically, memory cells have a matrix structure consisting of rows and columns and a memory for an intermediate word size can have either X rows or X columns, or both, where X is between the Nth power of 2 and the (N−1)th power of 2. In the following examples, it is assumed that the number of rows is X, where X is between the Nth power of 2 and the (N−1)th power of 2, because the number of rows is used more frequently. Moreover, though the present invention can be applied to any memory as long as it has memory cells arranged in a matrix form, an SRAM is used as an example here.
The memory for an intermediate word size shown in
FIG. 2
is equipped with memory cells
11
having X rows, where X is between the Nth power of 2 and the (N−1)th power of 2, dummy memory cells
12
that produce output “H” or “L” when rows larger than X (surplus address) are accessed, column gate
13
, data input/output circuit
14
, row address buffer (or row address register)
15
, column address buffer (or column address register)
16
, row decoder
17
, column decoder
18
, and surplus address detection circuit
19
that detects accesses to rows larger than X and activates dummy memory cells
12
. This memory is the same as the normal memory with the exception of dummy memory cells
12
and surplus address detection circuit
19
.
Surplus address detection circuit
19
is a logic circuit to which row address signals sent from row address buffer
15
are supplied, detects accesses to the surplus addresses by logical operation of row address signals, and puts out dummy memory cell activating signals that activate the word line of dummy memory cells
12
. Dummy memory cells
12
have the same structure as normal memory cells and the dummy memory cell activating signals are applied to the word line. The nodes of the memory cells (flip-flop) are connected to “H” or “L” so that the stored value is “H” or “L”.
As mentioned above, the number of process steps required to manufacture semiconductor devices can be reduced by designing a basic circuit configuration in advance and modifying it according to an individual purpose. It is preferable if the modification is minor, however, the maximum word row can be specified for any given number X between the Nth power of 2 and the (N−1)th power of 2 in a memory for an intermediate word size, and it is required for surplus address detection circuit
19
to detect accesses to addresses (surplus address) larger than the specified maximum word row number X. Therefore, there can be diverse surplus address detection circuits according to the maximum word row number X, and each surplus address detection circuit has been designed separately to meet the maximum word row number, resulting in excessive process steps.
On the other hand, a layout space for the surplus address detection circuit is generally limited and a smaller area for the circuit is preferable. This prevents surplus address detection circuit
19
from accepting all row address signals, and is a factor that has impeded the development of a general purpose surplus address detection circuit that can be used for diverse maximum word row numbers.
SUMMARY OF THE INVENTION
The present invention aims at the development of a smaller surplus address detection circuit for various purposes that can be used for diverse maximum word row numbers in semiconductor devices equipped with a memory for an intermediate word size by solving these problems.
For this purpose, the surplus address detection circuit is designed so as to detect accesses to surplus addresses by outputs of pre-decoders, which are constituents of the decoder, and only a part of the outputs of plural pre-decoders is supplied to the surplus address detection circuit.
The semiconductor device of the present invention, which comprises a memory for an intermediate word size having X rows or columns, where x is between the Nth power of 2 and the (N−1)th power of 2 and N is a natural number, an address decoder that decodes address signals indicating row or column locations of the memory for an intermediate word size to be accessed, and a surplus address detection circuit that detects accesses by address signals to surplus addresses larger than X, is characterized in that: the address decoder comprises plural pre-decoders that decode address signals classified into plural smaller groups and a post-decoder that generat

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