Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-03-10
2001-10-09
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S394000
Reexamination Certificate
active
06300655
ABSTRACT:
This application is based on Japanese patent applications HEI 10-61709 filed on Mar. 12, 1998 and HEI 11-39079 filed on Feb. 17, 1999, the whole contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture, and more particularly to a semiconductor device with memories of high integration and its manufacture.
b) Description of the Related Art
Still higher integration is required for semiconductor integrated circuit devices. Requirements of high integration are particularly strong in dynamic random access memory (DRAM) devices.
One memory cell of DRAM is generally constituted of one memory capacitor and one transistor. A transistor used is generally an insulated gate (IG) field effective transistor (FET) having a pair of source/drain regions, a channel coupling the source/drain regions, and an insulated gate electrode disposed above the channel for controlling the conductivity of the channel The IG FET is typically a metal-oxide-semiconductor (MOS) FET.
A memory capacitor is connected to one (hereinafter called a source, as a matter of convenience) of source/drain regions, and a bit line is connected to the other hereinafter called a drain as a matter of convenience). A word line is connected to the insulated gate electrode. In order to realize high integration, it is desired to make memory cells of a fine pattern and dispose a plurality of bit lines and word lines at a narrow pitch. Various techniques have been proposed to dispose bit and word lines at a high density.
It is also desired that DRAM has excellent retention (storage) characteristics which show how long electric charges in the capacitor can be retained.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device having memory cells suitable for high integration and excellent in retention characteristics.
It is another object of the invention to provide a method of manufacturing such semiconductor devices.
According to one aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate having one principal surface and a first conductivity type surface area exposed to the principal surface; an element isolation insulating region formed on the principal surface of the semiconductor device and defining a plurality of active regions in the first conductivity type surface area; a gate insulating film formed on a partial surface of each of the plurality of active regions; a plurality of word lines each partially disposed on the gate insulating film on the principal surface and made of conductive material, each of the plurality of word lines extending in a first direction as a whole; a plurality of bit lines extending in a second direction as a whole intersecting with the first direction on the principal surface; a plurality of capacitors formed on the principal surface; and a plurality of memory cell transistors formed in the plurality of active regions, each memory cell using one word line as a gate electrode and having a pair of source and drain regions of a second conductivity type opposite to the first conductivity type, the source and drain regions being defined by the gate electrode and the element isolation insulating region, one of the pair of source and drain regions being connected to one of the plurality of bit lines, the other of the pair of source and drain regions being connected to one of the plurality of capacitors, three sides of an area of the other of the pair of source and drain regions being defined by the element isolation insulating region, and the other of the pair of source and drain regions including a first impurity doped region extending to a location under another word line adjacent to the one word line and a second impurity doped region partially overlapping the first impurity doped region and the gate electrode.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming an element isolation insulating film on a principal surface of a first conductive type area of a semiconductor substrate, the element isolation insulating film defining an active region; selectively introducing impurities of a second conductivity type opposite to the first conductivity type into end portions of the active region to form first impurity doped regions; forming a gate insulating film on the active region; forming a word line made of conductive material on the gate insulating film, a pattern of the word line not overlapping the first impurity doped region, traversing the active region, and extending in one direction; introducing impurities of the second conductivity type into the active region by using the word line and the element isolation insulating film as a mask, to form second impurity doped regions at least partially overlapping the first impurity doped regions; and forming a capacitor connected to one of the second impurity doped regions and extending over the word line.
The region having the same conductivity type as that of the source/drain regions of a memory transistor is formed under the adjacent word line. Therefore, irrespective of any potential of the adjacent word line, it is possible to prevent generation of a depletion layer or an inversion layer so that deterioration of the retention characteristics to be caused by the potential of the adjacent word line can be reduced.
As above, the retention characteristics of a DRAM type memory cell can be improved.
REFERENCES:
patent: 4970564 (1990-11-01), Kimura et al.
patent: 5365095 (1994-11-01), Shono et al.
patent: 5457064 (1995-10-01), Lee
patent: 5732009 (1998-03-01), Tadaki et al.
patent: 7-273181 (1995-10-01), None
Ema Taiji
Hashimoto Koichi
Armstrong Westerman Hattori McLeland & Naughton LLP
Fujitsu Limited
Prenty Mark V.
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