Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2001-02-20
2001-10-16
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S781000
Reexamination Certificate
active
06303524
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the formation of low dielectric constant (“low k”) layers suitable for use in semiconductor devices, and more particularly, to a method for curing low k dielectric materials using very short, relatively high temperature cycles.
2. Background of the Invention
Semiconductor chips are used in many applications, including as processor chips for computers, as integrated circuits, and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, ideally a semiconductor chip holds as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips are minimized, while nevertheless improving the memory capacity and computing power of the devices. The escalating requirements for high density and performance associated with ultra-large scale integration semiconductor devices necessitate design features of 0.18 micron and under, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput.
A common circuit component of semiconductor chips is the transistor. In ultra-large-scale integrated (ULSI) semiconductor chips, a transistor is established by forming a polysilicon gate on a silicon substrate, and then forming a source region and a drain region side by side in the substrate beneath the gate by implanting appropriate dopant materials into the areas of the substrate that are to become the source and drain regions. The gate is insulated from the source and drain regions by a thin gate oxide layer. This generally-described structure cooperates to function as a transistor.
A conventional method for forming patterned metal layers comprises a subtractive etching or etch back step as the primary metal forming technique. Such a method involves forming a first dielectric layer on a semiconductor substrate, typically a monocrystalline silicon (Si) wafer, with conductive contacts formed therein for electrical connection with at least one active region formed in or on the substrate, such as a source/drain region of a transistor. A metal layer is deposited on the first dielectric layer and patterned using photolithographic masking and etching techniques to form a desired conductive pattern comprising a metal feature separated by gaps, such as a plurality of metal lines with inter-wiring spacings therebetween. A dielectric layer is then applied to the resulting conductive pattern to fill in the gaps. The surface thereof is then planarized by conventional etching or chemical-mechanical polishing (CMP) techniques.
A through-hole is then formed in the dielectric layer to expose a selected portion of an underlying metal feature. The exposed portion of the metal feature at the bottom of the through-hole serves as a contact pad. Upon filling the through-hole with conductive material, such as a metal plug, to form a conductive via, the bottom surface of the conductive via is in electrical contact with the underlying metal feature.
Many ultra large scale integration (ULSI) devices presently manufactured are very complex and require multiple levels of metallization for interconnections. It has been common to repeat the above-described via formation process multiple times, e.g., to form five levels of metallization interconnected by conductive vias, with each level of metallization separated by at least one layer of dielectric material, termed an inter-level dielectric (ILD) layer.
As semiconductor devices become smaller, and on-chip device density correspondingly increases, signal delays due to capacitive coupling and crosstalk between closely spaced metal lines are increasing. These problems are exacerbated by the need to keep conductor lines as short as possible in order to minimize transmission delays, thus requiring multi-level wiring schemes for the chip. As a consequence, capacitive coupling between conductive lines significantly limits circuit speed. A problem encountered in highly miniaturized semiconductor devices employing multiple metallization levels and reduced inter-wiring spacings in both the horizontal and vertical dimensions is related to the resistance-capacitance (RC) time constant of the system. If intra-metal capacitance is high, electrical inefficiencies and inaccuracies increase. It has been recognized that a reduction in capacitance within the multi-level metallization system will reduce the RC time constant between the conductive lines. The use of an insulator with a lower dielectric constant than the silicon dioxide (k=3.9) that is currently used could improve the situation. (The dielectric constant is based on a scale where 1.0 represents the dielectric constant of a vacuum.) As used herein, the term “low k” will refer to materials that have dielectric constants less than 3.9.
The drive to reduce the RC delay associated with the metal interconnect lines also has led the industry to move away from the traditional aluminum (Al) interconnect metal lines in favor of copper (Cu) based metallization. The sheet resistivity of copper-based metal lines can be half that of aluminum-based metal systems. However, copper diffuses more easily into the inter-level dielectric at normal processing temperatures, thereby degrading the dielectric and weakening the isolation between adjacent metal lines. If the copper diffuses into the underlying silicon, then the device performance also will be degraded. To prevent unwanted diffusion, most copper processes (e.g., dual damascene process) add a refractory barrier metal layer (e.g., tantalum, tantalum nitride, titanium, titanium nitride, tungsten or tungsten nitride) between the copper and the inter-level dielectric. For very narrow copper lines, applying an appropriate refractory barrier metal layer is very important. Thick barrier layers can result in higher metal line resistance than found in Al lines. Therefore, the thickness of the barrier layer must be minimized.
The drive towards increased miniaturization and the resultant increase in the RC time constant also have served as an impetus for the development of newer, low dielectric constant (“low k”) materials as substitutes for conventional higher dielectric constant silicon oxide-based ILD materials. The ILD films or layers must normally be formed at relatively low temperatures in order to avoid damage to or destruction of underlying conductors. Lower processing temperatures can increase the time needed for layer formation leading to decreased manufacturing throughput. Another important consideration for RC time constant effects is that dielectric films used as ILD materials must have a low dielectric constant, as compared to the value for silicon dioxide (k=3.9), in order to reduce the RC time constant, lower the power consumption, reduce crosstalk, and reduce signal delays in closely spaced conductors.
One prior process for applying low k materials to semiconductor substrates is shown in U.S. Pat. No. 6,066,574. First, a layer of low k material resin combined with a solvent or dispersant therefor is applied to a substrate by a spin coating process. The coated substrate is then baked at a relatively low temperature, such as 140° C. to 180° C., and for a time interval to sufficient to remove the solvent or dispersant from the coating material, such as from 30 to 90 seconds. The coated substrate is then cured at 250° C. to 350° C. for up to 90 seconds to initiate polymerization or cross-linking sufficient to convert the low k coating material to a low dielectric constant coating layer having the desired properties. The substrate with the low dielectric constant coating layer thereon is then subjected to a cool-down treatment for 30 to 90 seconds at a temperature in the range of 20° C. to 120° C. The method shown in U.S. Pat. No. 6,066,574 makes use of hot plates as the heating means. Temperature ramp up and ramp down of the coated substrate is controlled by regulating the spacing between the hot plates and the substrate, and
Sharangpani Rahul
Tay Sing-Pin
Connolly Bove & Lodge & Hutz LLP
Mattson Thermal Products Inc.
Tsai Jey
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