Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-07-22
2001-11-20
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S302000, C257S627000, C257S628000
Reexamination Certificate
active
06320215
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor transistor devices and, more specifically, to DRAM cells having non-planar transistor channel regions.
BACKGROUND OF THE INVENTION
Dynamic Random Access Memory (DRAM) cells can retain information only temporarily, on the order of milliseconds, even with power continuously applied. Therefore, the cells must be read and refreshed at periodic intervals. Although the storage time may appear to be short, it is actually long enough to allow many memory operations to occur between refresh cycles. The advantages of cost per bit, device density, and flexibility of use (i.e., both read and write operations are possible) have made DRAM cells the most widely used form of semiconductor memory to date. The earliest DRAM cells were three-transistor cells. Today, DRAM cells consisting of only one transistor and one capacitor have been implemented.
As DRAM circuits are scaled to small dimensions, it becomes increasingly important to form compact array cell layouts. The active device transistor is placed along the vertical side wall of a deep-trench storage capacitor in one type of array cell layout. Such a configuration forms a non-planar transistor device.
The non-planar transistor channel region crystal orientation can be a function of lithographic-projected image shape and the overlay between lithographically defined deep trench and active area patterns. Gate oxide thickness, surface state density, and other physical and electrical properties may be a function of the projected image shape and the overlap between the deep trench and active area patterns. These physical and electrical properties influence the transistor electrical, physical, and reliability characteristics.
As shown in
FIG. 1
, a typical deep trench having an elliptical cross section has a vertical side wall
32
that cuts across a continuum of planes including {001} and {011} crystal planes. Side wall
32
is not aligned with any particular crystal plane. Therefore, side wall
32
has associated crystal-plane-dependent properties that vary as side wall
32
makes a curved transition from one crystallographic plane to the other.
In accordance with standard crystallographic nomenclature, various symbols have specified meanings. Among those symbols are rounded brackets, { }, which refer to families of equivalent crystallographic planes (i.e., the {001} family of planes); parentheses, ( ), which refer to specific crystallographic planes (i.e., the (100) plane); horizontal triangles, < >, which refer to families of equivalent crystallographic axes (i.e., the <011>family of axes); and square brackets, [ ], which refer to a specific crystal axis (i.e., the [110] axis). For example, in silicon crystals, the (100) plane and the (001) plane are equivalent to one another and, thus, are both in the same {001} family of planes.
For optimized device performance, it is desirable to provide a side wall device aligned to a single crystallographic plane having a crystallographic orientation along a single crystal axis. It is an object of the present invention, therefore, to provide a crystal-axis-aligned, non-planar transistor structure. A related object is to provide a process for obtaining such a structure.
SUMMARY OF THE INVENTION
To achieve these and other objects, and in view of its purposes, the present invention provides a dynamic random access memory (DRAM) cell. The cell comprises a deep trench storage capacitor having an active transistor device partially disposed on a side wall of the deep trench. The side wall is aligned to a first crystallographic plane having a crystallographic orientation along a single crystal axis. The substrate surface may be aligned along a second crystallographic plane. The first and second crystallographic planes may be in the same family of equivalent crystallographic planes, such as the {001} family, or the first and second crystallographic planes may be in different families.
The present invention also provides a process for manufacturing a DRAM cell. The process comprises: (a) forming a deep trench in a substrate, (b) forming a faceted crystal region having a single crystallographic orientation along the trench side wall, and (c) forming a transistor device partially disposed on the faceted crystal region in the side wall. The faceted crystal region may be formed by growing an oxide collar, such as by local thermal oxidation under oxidation conditions selected to promote a higher oxidation rate along a first family of crystallographic axes, such as along the <011>family of crystal axes, than along a second family of crystallographic axes, such as along the <100>family of crystal axes. Other chemical and physical mechanisms may also be used to induce faceting in the trench side wall.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
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01065862 Mar. 13, 1989, Japan.
Bronner Gary
Gruening Ulrike
Mandelman Jack A.
Radens Carl J.
International Business Machines - Corporation
Ratner & Prestia
Tran Minh Loan
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