Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-12-01
2001-10-16
Ngô ;, Ngâ ;n V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S059000, C257S070000, C257S072000, C257S627000
Reexamination Certificate
active
06303963
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor thin film formed on a substrate having an insulating surface and a semiconductor device formed of a TFT having an active layer of the thin film. Particularly, the invention relates to a structure in a case where a material containing silicon as its main ingredient is used as a semiconductor thin film.
Incidentally, in the present specification, the term “semiconductor device” indicates any devices functioning by using a semiconductor, and the following are included in the category of the semiconductor device.
(1) Single device such as a thin film transistor (TFT).
(2) Semiconductor circuit using the single device of (1).
(3) Electro-optical device formed using (1) or (2).
(4) Electronic device (electronic equipment) including (2) or (3).
2. Description of the Related Art
In recent years, attention has been paid to a technique for constructing a thin film transistor (hereinafter referred to as a “TFT”) by using a semiconductor thin film (its thickness is several tens to several hundreds nm) formed on a substrate having an insulating surface. The thin film transistor is widely used for an electronic device such as an IC or an electro-optical device, and particularly as a switching element of an image display device, its development has been hastened.
For example, in a liquid crystal display device, an attempt to apply the TFT to any electric circuits, such as a pixel matrix circuit for controlling each of pixel regions arranged in matrix form, a driver circuit for controlling the pixel matrix circuit, and a logic circuit (a processor circuit, a memory circuit, etc.) for processing a data signal from the outside, has been made.
Under the present circumstances, although a TFT using a noncrystalline silicon film (amorphous silicon film) as an active layer has been put to practical use, a TFT using a crystalline silicon film (typically, a polysilicon film, a polycrystalline silicon film, etc.) is necessary for an electric circuit expected to have further high speed operating performance, such as a driver circuit and a logic circuit.
For example, as a method of forming a crystalline silicon film on a glass substrate, techniques disclosed in Japanese Patent Laid-Open Application No. Hei. 7-130652 and No. Hei. 8-78329 by the present applicant are well known. The techniques disclosed in these publications use a catalytic element for promoting crystallization of an amorphous silicon film, so that formation of a crystalline silicon film superior in crystallinity is made possible by a heat treatment at 500 to 600° C. for about 4 hours.
Particularly, the technique disclosed in Japanese Patent Laid-Open Application No. Hei. 8-78329 is such that crystal growth almost parallel to a substrate surface is made by applying the above techniques, and the present inventor et al. refer to a formed crystallized region especially as a side growth region (or a lateral grow region).
However, a TFT has a defect that fluctuation in electric characteristics (characteristic fluctuation) is large as compared with a MOSFET formed on a silicon wafer. Thus, it is difficult to reproduce the same characteristics even if TFTs have the same structure, which has made it difficult to form a circuit with the TFTs.
A technique for forming a high performance TFT with less characteristic fluctuation becomes necessary for realization of a system-on-panel at which the present applicant is aiming. That is, in order to realize the system-on-panel, it is necessary to use a TFT in which not only an operating speed is high (electric field mobility is large) but also fluctuation in electric characteristics representing a TFT, such as a threshold voltage and a subthreshold coefficient, is suppressed.
SUMMARY OF THE INVENTION
The present invention has been made in response to the foregoing request, and an object of the invention is to provide a method of fabricating a TFT having high performance and less fluctuation in characteristics, which can form such a high performance semiconductor circuit that its fabrication using a conventional TFT has been impossible.
Another object of the invention is to provide a semiconductor circuit and an electro-optical device formed of such TFTs, and an electronic device having those as parts.
The constitution of the present invention is as follows.
A semiconductor device having a circuit including a plurality of TFTs formed on a same substrate, wherein:
in a channel formation region of each of the plurality of TFTs, a plane orientation exhibits a {110} orientation, and 90% or more of crystal lattices have continuity at crystal grain boundaries; and
when a collective of threshold voltages (Vth) exhibited by the plurality of the respective TFTs is made a population, a standard deviation (&sgr;) is 0.1 V or less.
Further, a semiconductor device having a circuit including of a plurality of TFTs formed on a same substrate, wherein:
an electron beam diffraction pattern observed when an electron beam is vertically irradiated to a channel formation region of each of the plurality of TFTs exhibits regularity peculiar to a {110} orientation; and
when a collective of threshold voltages (Vth) exhibited by the plurality of the respective TFTs is made a population, a standard deviation (&sgr;) is 0.1 V or less.
Incidentally, in the above structure, the threshold voltage is a value of a dot where a tangential line having a maximum slope among tangential lines of a curve which is obtained by plotting gate voltages in an X axis and the square roots of drain currents in a Y axis (measurement is made at source voltage: 0 V, drain voltage: 11 V, and gate voltage: −20 to 20 V), intersects with the X axis. Such a method of obtaining a threshold voltage is generally referred to as a root ID extrapolation (ID is a drain current).
Another constitution of the present invention is as follows.
A semiconductor device having a circuit including of a plurality of TFTs formed on a same substrate, wherein:
in a channel formation region of each of the plurality of TFTs, a plane orientation exhibits a {110} orientation, and 90% or more of crystal lattices have continuity at crystal grain boundaries; and
when a collective of subthreshold coefficients (S-values) exhibited by the plurality of the respective TFTs is made a population, a standard deviation (&sgr;) is 10 mV/dec. or less.
Further, a semiconductor device having a circuit including of a plurality of TFTs formed on a same substrate, wherein:
an electron beam diffraction pattern observed when an electron beam is vertically irradiated to a channel formation region of each of the plurality of TFTs exhibits regularity peculiar to a {110} orientation; and
when a collective of subthreshold coefficients (S-values) exhibited by the plurality of the respective TFTs is made a population, a standard deviation (&sgr;) is 10 mV/dec. or less.
Incidentally, in the above structure, the subthreshold coefficient is a reciprocal of a slope of a tangential line having a maximum slope among tangential lines of a curve obtained by plotting gate voltages in an X axis and the square roots of drain currents in a Y axis (measurement is made at source voltage: 0 V, drain voltage: 1 V, and gate voltage: −20 to 20 V). In general, the coefficient is expressed by an equation of ln 10·kT/q[1+(Cd+Cit)/Cox]. Where, k is the Boltzmann constant, T is absolute temperature, q is an amount of electric charge, Cd is depletion layer capacitance, Cit is equivalent capacitance of interface level, and Cox is gate capacitance.
The present invention realizes a high performance TFT having features such as the foregoing structure, and realizes a high performance semiconductor device by forming a circuit using the TFT.
REFERENCES:
patent: 5403772 (1995-04-01), Zhang et al.
patent: 5426064 (1995-06-01), Zhang et al.
patent: 5481121 (1996-01-01), Zhang et al.
patent: 5488000 (1996-01-01), Zhang et al.
patent: 5492843 (1996-02-01), Adachi et al.
patent
Koyama Jun
Ohtani Hisashi
Yamazaki Shunpei
Ngô ; Ngâ ;n V.
Nixon & Peabody LLP
Robinson Eric J.
Semiconductor Energy Laboratory Co,. Ltd.
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