Circuit for the switching of loads

Details Circuit for the switching of loads Circuit for the switching of loads

2000-05-09

2001-11-20

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Reliability

Redundant

C326S009000, C326S012000, C326S013000

Reexamination Certificate

active

06320405

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a circuit configuration for switching loads.
BACKGROUND OF THE INVENTION
In switching safety-relevant loads in the automotive field, for example, critical operating states due to a defect in the switch must absolutely be avoided. Therefore, in most cases circuit configurations having two independent series-connected semiconductor switches are used for switching such loads to create a certain redundancy. With this concept, one of the switches is used to switch the load while the other functions as an “emergency stop switch.” This “emergency stop switch” monitors the functionality of the switch that switches the load. No monitoring of the functionality of the “emergency stop switch” is provided here.
SUMMARY OF THE INVENTION
According to one aspect of an exemplary embodiment of the present invention, a circuit configuration having at least two series-connected MOSFET output stages, each can be controlled by a logic circuit, is proposed, with mutual monitoring of the two MOSFET output stages being implemented so that starting of the load is prevented in the event of a short circuit in one of the two MOSFET output stages.
According to one aspect of an exemplary embodiment of the present invention, the power supply voltage of the downstream MOSFET output stage is supplied over the first MOSFET output stage, so that a short circuit in the downstream MOSFET output stage can be detected simply by monitoring its power supply voltage when small test currents are supplied. Therefore, according to the present invention, means are provided that are activated by a starting signal (INPUT), and prevent activation of the first MOSFET output stage when the power supply voltage of the downstream MOSFET output stage is below a predetermined value.
To determine whether there is a short circuit in the first MOSFET output stage, in an exemplary embodiment of the present invention, a circuit configuration includes a connection line between the logic circuits of the two MOSFET output stages, with an input voltage being applied to the logic circuit of the downstream MOSFET output stage over this connecting line. Then when the first MOSFET output stage is activated on the basis of the INPUT signal, this input voltage is varied in a defined manner. In the case of a short circuit in the first MOSFET output stage, there is a sufficient power supply voltage for the downstream MOSFET output stage, but the input voltage applied to the system logic of the downstream MOSFET output stage differs from the input voltage defining the normal state. The fault case can thus be detected easily, and activation of the downstream MOSFET output stage and thus of the load can be prevented.
According to one aspect of an exemplary embodiment of the present invention a circuit configuration permits parallel monitoring of the functionality of both MOSFET output stages. The load is prevented from starting when there is a defect in one of the two MOSFET output stages, so critical operating states of the downstream load can be prevented reliably.
In an advantageous embodiment of the circuit configuration In an exemplary embodiment of the present invention, in addition to taking into case of simultaneous damage to the respective system logic is also taken into account and starting of the load is also prevented in this case. The circuit configuration according to in exemplary embodiment of the present invention or the system logic of the first MOSFET output stage has means for clocking the input voltage. With the help of the system logic of the downstream MOSFET output stage, the switching edges in the input voltage signal are detected and the load is switched off in the absence of switching edges. Thus, the functionality of the system logic of the first MOSFET output stage is also tested by analyzing the clock pulse of the input signal.
In terms of circuit logic, there are now various options for implementing the individual functions described above for the circuit configuration according to the present invention for switching loads. Especially advantageous embodiments of the present invention are illustrated in the drawings and explained in greater detail in the following description. The drawings show:


REFERENCES:
patent: 5216293 (1993-06-01), Sei et al.
patent: 5367205 (1994-11-01), Powell
patent: 5598119 (1997-01-01), Thayer et al.
patent: 39 24 988 A (1991-01-01), None
patent: 43 21 971 A (1994-01-01), None
patent: 0 609 158 A (1994-08-01), None
patent: 0 717 497 A (1996-06-01), None

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