Generalized address generation for bit reversed random...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...

Reexamination Certificate

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C714S761000, C714S762000, C714S787000, C714S788000

Reexamination Certificate

active

06314534

ABSTRACT:

BACKGROUND OF THE INVENTION
I. Field of the Invention
The present invention relates to communications. More particularly, the present invention relates to novel and improved method and apparatus generating memory addresses in an interleaver.
II. Description of the Related Art
Turbo coding is a very powerful form of forward error correction (FEC) coding. Forward error correction involves correcting errors in transmitted data. To perform error correction, the FEC coding is applied to the data before transmission. Once received, the original data is recovered from the received data using a decoding process. Providing this type of error correction allows successful transmission of data in noisy environments, and therefore facilitates various types of digital communication.
SUMMARY OF THE INVENTION
The present invention is a novel and improved method and apparatus for address generation in an interleaver. In accordance with one embodiment of the invention, an address is generated using a random address fragment and a bit reversed address fragment. A bit reversed address fragment is selected by first generating two consecutive candidate bit reversed fragments. A second bit interleaved fragment is selected when the first bit interleaved address fragment generates an address that is greater than a maximum address. The address generator allows address generation for interleaver and deinterleaver frame sizes of N, where N is not an integer power of two, without any cycle penalty.


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Hanan Herzberg, “Multilevel Turbo Coding with Short Interleavers”, IEEE Journal on Selected Areas in Communications, vol. 16, No. 2, Feb. 1998.

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