Semiconductor memory device and signal line shifting method

Details Semiconductor memory device and signal line shifting method Semiconductor memory device and signal line shifting method

2000-08-28

2001-10-23

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230060, C365S240000

Reexamination Certificate

active

06307794

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor memory device, such as a DRAM, and a signal line shifting method.
More specifically, the invention relates to a semiconductor memory device and signal line shifting method using a column redundant system for replacing a data line, to which data of a defective column is outputted, with a remaining normal data line and a spare data line by shifting the data line.
2. Related Background Art
Conventionally, in order to relieve defective bits to improve the yield of DRAMs or the like, a redundant circuit system for arranging a redundant cell array for a specific memory cell array is adopted. In a standard redundant circuit system, a fuse circuit for storing defective addresses is mounted in a chip. Then, when a defective address is inputted, the coincidence of the inputted defective address with a defective address stored in the fuse circuit is detected to output a substitution signal. By this signal, a substitution control for selecting a redundant column or a redundant row in place of a defective column or a defective row is carried out.
However, in this conventional redundant circuit system, it is necessary to establish a one-to-one correspondence between defective columns and redundant columns, and thus there is a disadvantage in that it is necessary to provide many redundant circuits in order to enhance the defective relieving efficiency.
On the other hand, as a redundant circuit system for efficiently relieving defective columns by a smaller number of redundant circuits, a system utilizing a data line shift has been proposed (e.g., Japanese Patent Laid-Open No. 3-176899 and No. 5-101648). In this system, when a defective column address is inputted, a data line, to which data of the defective column should be outputted, is avoided, and the next normal data line is used. Subsequently, a data line shift control for sequentially shifting data lines one by one to connect only normal data lines, which include one spare data line arranged on the end portion of the arrangement of data lines, to data input/output lines is carried out.
However, in the defective column relieving system based on the data line shift, if the starting point of the data line shift corresponding to the defective column address is stored to carry out the shift control, when the number of data input/output lines (I/O lines) is large, the number of selecting signal lines for the shift control is large, and as a result the construction of a multiplexer part for the data line shift is complicated.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a semiconductor memory device using a defective column relieving system wherein the number of selecting signal lines for data line shift control is small.
In order to accomplish the aforementioned, and other objects, according to one aspect of the present invention, a semiconductor memory device comprising: a memory cell array having memory cells arranged in the form of a matrix; a redundant column cell array configured to relieve a defective column of the memory cell array; a decoder circuit configured to decode an address to select a memory cell in the memory cell array; a plurality of data lines, to which data read out from the memory cell array or data to be written in the memory cell array, corresponding to a plurality of columns, is transferred by the decoder circuit; a spare data line, to which data read out from the redundant column cell array or data to be written in said redundant column cell array is transferred; a data line shift circuit configured to shift, one by one, data line and the spare data line, which are arranged on one side of a data line serving as a starting point, to which data of a defective column is to be transferred when the defective column is accessed, to connect the data lines and the spare data line to data input/output lines; a selecting circuit configured to store a correspondence between an address of the defective column and a shift point, which is assigned to each of the data input/output lines so as to increase by 1 of every starting point of the data line shift by the data line shift circuit, and output a selecting signal corresponding to the shift point when the address of the defective column is inputted; and a shift control circuit configured to output a shift control signal to the data line shift circuit by comparing the selecting signal, which is outputted from the selecting circuit, with the shift point.
According to a further aspect of the present invention, there is provided a semiconductor memory device comprising: a memory cell array having memory cells arranged in the form of a matrix; a redundant column cell array for relieving a defective column of the memory cell array; a decoder circuit for decoding an address to select a memory cell in the memory cell array; a plurality of data lines, to which data read out from the memory cell array or data to be written in the memory cell array, corresponding to a plurality of columns, is transferred by the decoder circuit; a spare data line, to which data read out from the redundant column cell array or data to be written in the redundant column cell array is transferred; and a data line shift circuit for shifting, one by one, data lines and the spare data line, which are arranged on one side of a data line serving as a starting point, to which data of a defective column is to be transferred when the defective column is accessed, to connect the data lines and the spare data line to data input/output lines; which further comprises first means for establishing a correspondence between addresses and starting points for data line shift, and second means for establishing a correspondence between data input/output line numbers and starting points for data line shift, wherein the first and second means are used for determining a form of data line shift, which is carried out by the data line shift circuit, with respect to an inputted address.
According to a further aspect of the present invention, there is provided a signal line shifting method for a semiconductor memory device which comprises a memory cell array, a redundant column cell array, first signal lines corresponding to the memory cell array, and a second signal line corresponding to the redundant column cell array, wherein when the signal line shifting method shifts, one by one, first signal lines, which are arranged on one side of a first signal line serving as a starting point corresponding to a defective column when the defective column is accessed, to connect the first signal lines and the second signal line to input/output lines, the signal line shifting method comprises the steps of: establishing a correspondence between addresses and starting points for signal line shift; establishing a correspondence between input/output line numbers and the starting points for signal line shift; and inputting a predetermined address to compare the correspondences with each other to determine a form of signal line shift on the basis of the compared result.


REFERENCES:
patent: 4228528 (1980-10-01), Cenker et al.
patent: 4598388 (1986-07-01), Anderson
patent: 5134584 (1992-07-01), Boler et al.
patent: 6104648 (2000-08-01), Ooishi
patent: 6115301 (2000-09-01), Namekawa
patent: 411250688-A (1999-09-01), None

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