Semiconductor device for protecting a semiconductor chip...

Details Semiconductor device for protecting a semiconductor chip... Semiconductor device for protecting a semiconductor chip...

2000-08-29

2001-11-20

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S173000, C257S546000, C257S587000

Reexamination Certificate

active

06320231

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device for protecting a semiconductor chip from damage due to electrostatic discharge (ESD). More specifically, the invention relates to effective measures against ESD which is applied to a semiconductor chip having a diffusion-layer structure in which high-concentration impurities are diffused into a low-impurity-concentration diffusion layer.
Generally ESD occurs when a semiconductor chip is conveyed by man or machine. When ESD occurs, a voltage of several hundreds of volts to several thousands of volts is applied between two terminals of the chip for a very short time. To protect the semiconductor chip from damage due to the ESD, an ESD protecting element is provided in the chip.
FIGS. 1
to
3
each illustrate an example of the structure of a prior art ESD protecting element. In these figures, the same components are denoted by the same reference numerals.
FIG. 1
shows an example of the use of a diode as the ESD protecting element. In
FIG. 1
, an input pad
100
is connected to an internal circuit (not shown) through an input buffer circuit
101
. A diode
103
is connected between the input buffer
100
and a power supply terminal
102
. A diode
104
is also connected between the input buffer
100
and a ground terminal
105
.
FIG. 2
shows an example of the use of diode-connected bipolar transistors
106
and
107
as the ESD protecting element, while
FIG. 3
shows an example of the use of diode-connected MOS transistors
108
and
109
as the ESD protecting element.
The ESD protecting elements shown in
FIGS. 1
to
3
perform the same operation, so that the operation will be described with reference to
FIG. 1
only. The power supply terminal
102
and ground terminal
105
of a semiconductor chip are in a floating state during the conveyance of the chip because no power supply voltage is applied to the terminals
102
and
105
. When a discharge occurs between the input pad
100
and power supply terminal
102
, the potential of the input pad
100
becomes higher than that of the power supply terminal
102
or the potential of the power supply terminal
102
becomes higher than that of the input pad
100
. If the potential of the input pad
100
is higher than that of the power supply terminal
102
, a forward current flows through the diode
103
. If the potential of the power supply terminal
102
is higher than that of the input pad
100
, the diode
103
breaks down and a current flows from the power supply terminal
102
to the input pad
100
.
Similarly, when a discharge occurs between the input pad
100
and the ground terminal
105
, the diode
104
causes a forward current to flow or breaks down to protect an internal circuit in accordance with the relationship in potential between the input pad
100
and the ground terminal
105
.
When the semiconductor chip normally operates, i.e., when the potential VPAD of the input pad
100
satisfies the following expression (i), the ESD protecting element (diode
103
) between the input pad
100
and power supply terminal
102
turns off and so does the ESD protecting element (diode
104
) between the input pad
100
and ground terminal
105
. This does not exert an influence upon the operation of the semiconductor chip.
Vss≦VPAD≦Vcc
  (
i
)
where Vcc is a power supply voltage and Vss is a ground voltage.
FIGS. 4A and 4B
are plan and sectional views of ESD protecting elements each constituted of a bipolar transistor.
FIGS. 5A and 5B
are also plan and sectional views of ESD protecting elements constituted of a MOS transistor. In
FIGS. 4A and 4B
, a p-type well region
110
a
is formed in an n-type semiconductor substrate
110
. A collector region (C)
111
, an emitter region (E)
112
, and a base region (B)
113
, which are each constituted of an impurity diffusion layer, are formed in the well region
110
a
. These regions
111
,
112
and
113
are separated from each other by an STI (shallow trench isolation)
114
. A plurality of contacts
115
,
116
and
117
, which are made of aluminum and tungsten, are formed in their respective regions
111
,
112
and
113
.
Referring to
FIGS. 5A and 5B
, a p-type well region
120
a
is formed in an n-type semiconductor substrate
120
. A MOS transistor is formed in the well region
120
a
. A drain region (D)
121
and a source region (S)
122
, which are constituted of an n-type impurity diffusion layer, are formed in the well region
120
a
. A gate electrode (G)
123
is formed above a channel region located between the drain and source regions
121
and
122
with a gate insulation film interposed therebetween. A plurality of contacts
124
and
125
constituted of aluminum and tungsten are formed in each of the drain and source regions
121
and
122
. A contact region
127
of a p-type diffusion layer, which is separated from the above MOS transistor by an STI
126
, is formed in the well region
120
a
. A plurality of contacts
128
are formed in the contact region
127
.
In the ESD protecting elements shown in
FIGS. 4A
,
4
B,
5
A and
5
B, distance DS (corresponding to a current path of each diffusion layer) between each of sides (a boundary between the diffusion layer and the STI) of the diffusion layer constituting each of the collector region
111
, emitter region
112
, base region
113
, drain region
121
, source region
122
, and contact region
127
and each of the contacts
115
,
116
,
117
,
124
,
125
and
128
is set as long as possible for the following two reasons:
(1) When ESD occurs, a breakdown is easy to occur on the sides of the diffusion layer. For example, as illustrated in
FIG. 4B
, a breakdown occurs on a boundary Z between the collector region
111
and STI
114
to generate heat. If the distance DS is short, the heat will be transmitted to the contacts
115
to
117
and cause damage thereto. To prevent this, the distance DS is lengthened.
(2) If the distance DS is short, a current flows nonuniformly between each of the contacts and each of the sides of the diffusion layer. In other words, a current flows through a path whose resistance is the lowest (in the shortest distance). The current is therefore concentrated on a portion of the diffusion layer with a short distance D, and this portion is damaged. If the distance DS is lengthened, a current flows most uniformly between each of the contacts and each of the sides of the diffusion layer to prevent the diffusion layer from being damaged.
The optimum distance DS varies from process to process. For example, the distance DS is about 3 &mgr;m to 4 &mgr;m in the 0.25 &mgr;m process. This value is about ten times as large as the minimum value (design rules) of the distance between the contacts and the diffusion layer which depends upon reasons of processing.
The above diffusion layer is one connected to an input pad. It is known that to lengthen the distance between each contact and each side of a diffusion layer connected to a power supply terminal does not contribute to an improvement of resistance of ESD protecting elements (C. Duvvury, R. Rountree, D. Baglee, A. Hyslop, L. White, “ESD Design Considerations for ULSI,” EOS/ESD Symp. Proc., p45, 1985).
As semiconductor chips decrease in size, a diffusion layer tends to be thinned by the scaling law. At a contact portion between a contact and a diffusion layer which are formed of metal such as aluminum and tungsten, the linearity (ohmic) of contact resistance has to be secured and the contact resistance itself has to be lowered. For this reason, conventionally, ions of the same polarity as that of the diffusion layer are rediffused from the opening of a contact.
In a diffusion layer
131
of an N-channel MOS transistor as shown in
FIG. 6
, an n+ layer
133
whose impurity concentration is high is formed directly under a contact
132
so as to protrude from the diffusion layer
131
. A breakdown therefore occurs in the n+ layer
133
. In a semiconductor chip having such a diffusion layer, it is not effective to form an ESD protec

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