CMOS semiconductor device

Details CMOS semiconductor device CMOS semiconductor device

2000-01-19

2001-11-20

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S368000, C257S371000, C257S374000, C257S379000, C257S401000

Reexamination Certificate

active

06320233

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a CMOS semiconductor device, particularly, a CMOS transistor having an element isolating region of STI (Shallow Trench Isolation) structure. The CMOS semiconductor device of the present invention is used for manufacturing a CMOS type LSI.
FIG. 6A
is a plan view showing a CMOS transistor having an element isolating region of the conventional STI structure.
FIG. 6B
is a cross sectional view along the line
6
B—
6
B shown in FIG.
6
A. As shown in the drawings, the CMOS transistor comprises a P-type semiconductor substrate (P-substrate)
40
. An N-well
41
is selectively formed in a surface region of the P-substrate
40
. Also, a P-well
42
is formed adjacent to the N-well
41
. A PMOS transistor is formed in the N-well
41
, and an NMOS transistor is formed in the P-well
42
.
A source region
43
and a drain region
44
of the PMOS transistor are selectively formed in a surface region of the N-well
41
. Each of these source region
43
and the drain region
44
consists of a P
+
diffusion layer. A gate electrode
45
is formed above a channel region between the source region
43
and the drain region
44
of the PMOS transistor with a gate insulating film
46
interposed therebetween.
A shallow N-well leading region
47
made of an N-type diffusion region is selectively formed in a surface region of the N-well
41
. The shallow N-well leading region
47
is used for applying a bias potential (power source potential VDD) to the N-well
41
.
An STI region
48
is formed in a surface region of the N-well
41
in a manner to be sandwiched between the P
+
source
43
and the shallow N-well leading region
47
.
A source region
51
and a drain region
52
of the NMOS transistor are selectively formed in a surface region of the P-well
42
. Each of these source region
51
and the drain region
52
made of an N
+
diffusion region. A gate electrode
53
is formed above a channel region between the source region
51
and the drain region
52
of the NMOS transistor with a gate insulating film
54
interposed therebetween.
A shallow P-well leading region
55
made of a P-diffusion region is selectively formed in a surface region of the P-well
42
. The shallow P-well leading region
55
is used applying a bias potential (ground potential VSS) to the P-well
42
.
An STI region
56
is formed in a surface region of the P-well
42
in a manner to be sandwiched between the N
+
source region
51
and the shallow P-well leading region
55
.
Another STI region
57
is formed at the boundary between the N-well
41
and the P-well
42
in a manner to be sandwiched between the drain region
44
of the PMOS transistor and the drain region
52
of the NMOS transistor. The STI region
57
serves to isolate the PMOS transistor from the NMOS transistor and, thus, acts as a CMOS transistor isolating region.
STI regions
58
and
59
are formed at the boundary regions of the N-well
41
and the boundary regions of the P-well
42
, respectively, for isolating these N-well
41
and P-well
42
from other element regions. The CMOS transistor is isolated from the other elements by these STI regions
58
and
59
.
In the CMOS transistor of the construction described above, a distance al shown in
FIG. 6A
consists of a distance d
1
between the N-well
41
and an N
+
SDG (Source Drain Gate) region
60
constituting an active region of the NMOS transistor and a distance d
2
between the P-well
42
and a P
+
SDG region
50
constituting an active region of the PMOS transistor.
The design criteria of the distance d
1
between the N-well
41
and the N
+
SDG region
60
are determined in view of the breakdown voltage between the N-well
41
and the N
+
SDG region
60
, the nonuniformity in the size of the N
+
SDG region
60
, the nonuniformity in the size of the N-well
41
, the pattern aligning accuracy between the N-well
41
and the N
+
SDG region
60
, etc. Therefore, it is necessary to ensure a very large space for the distance d
1
between the N-well
41
and the N
+
SDG region
60
.
Likewise, the design criteria of the distance d
2
between the P-well
42
and the P
+
SDG region
50
are determined in view of the breakdown voltage between the P-well
42
and the P
+
SDG region
50
, the nonuniformity in the size of the P
+
SDG region
50
, the nonuniformity in the size of the P-well
42
, the pattern aligning accuracy between the P-well
42
and the P
+
SDG region
50
, etc. Therefore, it is necessary to ensure a very large space for the distance d
2
between the P-well
42
and the P
+
SDG region
60
.
As a result, the space between the P
+
SDG region
50
and the N
+
SDG region
60
, in which the CMOS transistor isolating region
57
is interposed, requires a large design criterion. It follows that the semiconductor device includes a large useless space in which the transistor itself is not arranged, making it difficult to further miniaturize the element.
As described above, the conventional CMOS transistor is constructed to include a large space between the active region of an NMOS transistor and the active region of a PMOS transistor with a CMOS transistor isolating region interposed therebetween. It follows that the conventional CMOS transistor includes a large useless region in which the transistor itself is not arranged, making it difficult to further miniaturize the element.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention, which has been achieved in an attempt to overcome the above-noted problems inherent in the prior art, is to provide a CMOS semiconductor device capable of moderating the limitations required in miniaturizing the element so as to diminish the pattern size of the CMOS transistor and the CMOS element region.
The particular object can be achieved by various means in the present invention as summarized below.
According to a first aspect of the present invention, there is provided a CMOS semiconductor device, comprising a semiconductor substrate of a first conductivity type; a well region of a second conductivity type formed selectively in a surface region of the semiconductor substrate; a first shallow well region of the second conductivity type formed selectively in a surface region of the well region in a manner to partly overlap with the well region; a source region and a drain region of a first MOS transistor, the source and drain regions made of diffusion regions of the first conductivity type selectively formed in a surface region of the first shallow well region; a first gate electrode formed above a channel region between the source region and drain region of the first MOS transistor with a gate insulating film interposed therebetween; a first shallow well leading region made of a diffusion region of the second conductivity type selectively formed in a surface region of the well region; a first shallow trench isolating region formed in a surface region of the well region, the first shallow trench isolating region being deeper than the first shallow well region, between the diffusion region of the first conductivity type of the first MOS transistor and the first shallow well leading region; a source region and a drain region of a second MOS transistor made of diffusion regions of the second conductivity type that are formed in a surface region of the semiconductor substrate; a second gate electrode formed above a channel region between the source region and drain region of the second MOS transistor with a gate insulating film interposed therebetween; and a second shallow trench isolating region for separating the CMOS transistor formed in a surface region of the semiconductor substrate, the second shallow trench isolating region being deeper than the first shallow well region, between the first shallow well region and the diffusion region of the second conductivity type of the second MOS transistor.
It is possible for the CMOS semiconductor device according to the first aspect of the pr

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