Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1997-08-27
2001-02-06
Santamauro, Jon (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S039000
Reexamination Certificate
active
06184710
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to programmable logic array integrated circuit devices, and more particularly to the interconnection conductor resources provided on such devices.
Programmable logic devices which perform combinatorial logic functions based on product term (“Pterm”) logic are well known as is shown, for example, by Pedersen et al. U.S. Pat. No. 5,241,224 and Patel et al. U.S. Pat. No. 5,371,422. Programmable logic devices which perform combinatorial logic functions based on look-up table logic are also well known as is shown, for example, by Cliff et al. U.S. patent application Ser. No. 08/672,676, filed Jun. 28, 1996. All of these references are hereby incorporated by reference herein.
The above-mentioned Cliff et al. reference shows a programmable logic device architecture in which so-called subregions of programmable logic are grouped together in so-called regions of programmable logic. Although other implementations are possible, in the especially preferred embodiment shown by Cliff et al. each subregion includes (1) a four-input look-up table for performing combinatorial logic on as many as four inputs to the subregion, (2) a register, and (3) programmable logic connectors (“PLCs”) for allowing the subregion to output the look-up table output either directly or as registered by the register. The Cliff et al. subregions may also have other capabilities, but the foregoing simplified description will be sufficient for present purposes.
An advantageous feature of the Cliff et al. architecture is that local interconnection conductors are interspersed or interleaved between adjacent regions. These local conductors bring signals to the adjacent regions from other longer-distance interconnection conductors such as those that extend along an entire row or column of regions on the device. The local conductors also receive the output signals of the adjacent regions and convey those signals to the longer-distance conductors. Each subregion in a region receives some of its inputs from the local conductors on each side of the region that includes that subregion. Thus each subregion can receive as an input via the adjacent local conductors the output of any subregion in the region that includes that subregion and any subregion in either of the regions that share local conductors with the region that includes that subregion. To illustrate the last portion of the preceding sentence, a subregion in a first region can output to a local conductor that is interleaved between the first region and an adjacent second region. A subregion in the second region can derive one of its inputs from that local conductor. Data can thereby travel very rapidly between adjacent regions using local conductors interleaved between those regions and without having to make use of the inherently somewhat slower longer-distance conductors.
The above-described advantage of look-up table based programmable logic devices with interleaved local conductors does not generalize very well to Pterm based devices. This is because in Pterm logic the input signals do not divide among the various macrocells very completely. Many input signals may be required to feed large numbers of Pterms.
In view of the foregoing, it is an object of this invention to provide Pterm logic with local interconnections between logic regions comparable to the local interconnections that are provided by the local conductors that are interleaved between the logic regions in devices of the type shown in the above-mentioned Cliff et al. reference.
It is a more general object of this invention to provide improved architectures for programmable logic devices, especially those that employ Pterm logic, but in some cases also those employing other types of logic such as look-up tables.
SUMMARY OF THE INVENTION
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing programmable logic devices having plural regions of programmable Pterm logic and a network of general-purpose inter-region interconnection conductors that is usable to convey signals to, from, and between the regions. Each region has an associated programmable interconnect array (“PIA”) which is programmable to select signals from the general-purpose interconnection conductor network for application to the programmable AND array of the region. The AND array of each region is programmable to produce various Pterms from its inputs. Some of the Pterms in each region are grouped into plural macrocells including several Pterms each. Other Pterms in each region may be used separately as so-called expander Pterms. Each macrocell also typically includes (1) an OR gate for logically combining at least some of the Pterms of the macrocell (to produce a sum-of-products output), (2) a register, and (3) a PLC (e.g., a switch or multiplexer) for allowing the macrocell to output the OR gate output either directly or as registered by the register. The macrocell outputs are connected to the general-purpose interconnection conductor network. The expander Pterms are fed back into the AND array producing those Pterms.
In order to provide the kind of more direct interconnections between adjacent regions that are provided by the interleaved local conductors in the above-mentioned Cliff et al. reference, at least some of the outputs of each region may be multiplexed with PIA outputs of one or more adjacent regions. The region outputs that are thus multiplexed onto the inputs of an adjacent region or regions may be some or all of the macrocell outputs of the first region, some or all of the expander Pterms of the first region, or some or all of both the macrocell outputs and expander Pterms of the first region.
An “adjacent” region in this discussion does not have to be an immediately adjacent region. Instead, it could be spaced some distance away, such as immediately adjacent to an immediately adjacent region.
With the foregoing definition of “adjacent” in mind, certain principles of this invention can also be applied to non-Pterm-type programmable logic devices such as look-up table devices of the type that are the main focus of the above-mentioned Cliff et al. reference. In such devices the outputs of a region can be multiplexed with local conductor inputs that are interleaved between two other nearby regions to make it possible to make direct connections between the first region and these two other regions.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.
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Altera Corporation
Fish & Neave
Jackson Robert R.
Santamauro Jon
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