Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1999-11-09

2001-02-27

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S316000, C365S185050, C365S185130, C365S185290

Reexamination Certificate

active

06194759

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory element, semiconductor memory device and control method therefore.
2. Prior Art
In the conventional art, non-volatile memory devices have been achieved such as flash EEPROM devices by utilizing MOSFET devices having floating gates and control gates. In such devices, information storage and readout are performed by utilizing the fact that the MOSFET threshold voltage changes when carriers accumulate on the floating gate. Polycrystalline silicon was generally utilized in the floating gate. Utilizing a MOSFET with floating gate allowed one bit of information to be stored for extended periods of time by use of only one transistor. A conventional structure and a contact-less cell structure are described in Nikkei Electronics, no. 444, pp. 151-157 (1988), as examples of flash EEPROM memory cell structures.
Technology of the conventional art relating to this invention is disclosed in K. Yanoetal, 1993 IEEE International Electron Devices Meeting, Digest of technical papers, pp. 541-545 and also in K. Yano et al, 1996 IEEE International Solid-State Circuits Conference, Digest of technical papers, pp. 266-267 and p. 458, describing single-electron memories utilizing polycrystalline silicon. In this technology, the channel which is an electrical path and a storage region to capture electrons are simultaneously formed of thin-film, polycrystalline silicon. Storage of information is performed by utilizing the change in threshold voltages when electrons are captured in the storage region. A feature of this method is that one bit is stored with the deposit of one electron. A smaller structure can be obtained, compared with a structure obtained by machining utilizing the crystal grains of polycrystalline silicon and the device of this method can also operate at room temperature.
In order to achieve the desired change in threshold voltage in flash EEPROM devices at carrier injection and drain (write, erase operation) to the floating gate, the memory state is monitored after application of a high voltage (or low voltage) and a verify operation is performed to once again apply a voltage to adjust the threshold values in cells where the desired threshold value was not obtained.
In the conventional art, technology for verify operations is disclosed in T. Tanaka et al. IEEE J. Solid-State Circuits, Vol. 29, No. 11, pp. 1366-1372 (1994) and in K. Kimura et al. IEICE Transactions on Electronics, Vol. E78-C No. 7, pp. 832-837 (1995).
Previous technology by the inventors of the present invention is disclosed in Japanese Patent Laid-open No. Hei 7-111295, No. Hei 8-288469, No. Hei 9-213822 and in Japanese Patent Laid-open No. Hei 9-213898.
SUMMARY OF THE INVENTION
Much progress by means of advances in lithographic technology has been made in reducing the surface area of memory cells for memory types such as DRAM, SRAM and flash memories. Memory cells configured with a smaller surface area offer many advantages such as decreasing the size of the chip to improve chip production yield and are effective in reducing costs since many chips can be obtained from the same wafer. A further advantage is that wiring length is kept short so that high-speed operation is possible.
The processing dimensions and cell size are generally determined by the memory method. If the basic machining dimension is set as F, then memory cell units are formed in a size such that a folding bit line type DRAM size is 8F2 and an AND type flash memory size is 6F2. Currently, the smallest cell sizes that can be fabricated have one cell of flash memory in one transistor and this standard is the approximate limit when forming MOS device structures on a substrate surface. When fabrication of even smaller memory cells is attempted, a cubic shaped structure becomes necessary. Further, once a smaller memory has been obtained by utilizing a cubic shape and the data line pitch or the word line pitch has been reduced to become shorter than a minimum of 2F, then how to arrange the data lines and word lines, how to connect to the peripheral circuits or how to control these cell arrays by means of the peripheral circuits become critical problems.
On the other hand, when inserting and extracting electrons in microscopic sized dots of metallic or semiconductor material, the coulomb repulsion force can be effectively utilized and a single electron element for controlling electrons in individual units are theoretically capable of operation in extremely small structures of approximately 10 nm and have advantages such as extremely small electric power consumption. A single-electronic memory consisting of a single-electron device is a memory capable of storing information as an accumulation of a small number of electrons. The single-electron memory can store one or more bits of information in one element and since control of the stored electrical charge can be performed in individual units, operation even down to the nanometer level is possible. Further, since the number of stored or accumulated electrons is small, a large improvement can be expected in terms of the rewrite time and the number of rewrites. However, in actual fabrication of the elements, the processing dimensions are subject to the current limits of lithographic technology. Still further, in elements of the conventional art, the size of extraction portions such as the drain region and source region is large and an element structure offering the advantage of integration providing a smaller size has not been proposed.
The inventors fabricated a single-electron memory operating at room temperatures and performed a device evaluation. However in that evaluation, various different times were measured for accumulating an electrical charge even if the same write voltage was applied to the same device for the same amount of time. Conversely, when the same write voltage was applied for the same amount of time, a phenomenon was discovered in which the number of electrons at one time was found to vary. This phenomenon was interpreted as occurring from probabilistic behaviors such as tunnel effect or heat excitation due to the small number of electrons utilized in operation of the single-electron memory.
Progress made in integration of semiconductor memories allowed improving the memory density and increasing the device capacity however the greater the integration of memory cells that was achieved in the device, the greater the equipment costs for manufacturing became. By performing multi-value storage for storing two or more bits in one cell, greater memory density becomes possible without performing further integration of memory cells. In multi-value storage, the ability to clearly distinguish the many memory states in write, read and erase operations is of the utmost importance.
Use of single-electron memories requires that the electrical charge be small and that the peripheral circuits generate little noise. Differential amplifiers are often utilized as sensing amplifiers for semiconductor memories. Here, methods are known for positioning the sensing amplifier and data line relative to each other so that the matching data lines are placed in an open configuration on both sides of the sensing amplifier, or in a folding configuration positioned in the same direction. The open configuration has the advantages that memory cells can be positioned at all cross points of the data lines and word lines and high integration can be obtained, however a disadvantage is that much noise is generated in the word lines. The folded configuration conversely, has the advantage that little noise is generated in driving the word lines yet also has the drawbacks that memory cells cannot be placed at all cross points of data lines and word lines; and further cannot offer high integration.
Peripheral circuits other than the sensing amplifier that have a large surface area are the register which temporarily holds write data in the memory cell during writing, a register to hold the flag showing write has ended during

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