Process for cutting trenches in a single crystal substrate

Details Process for cutting trenches in a single crystal substrate Process for cutting trenches in a single crystal substrate

1998-06-29

2001-10-16

Bowers, Charles (Department: 2823)

Semiconductor device manufacturing: process

Formation of semiconductive active region on any substrate

Amorphous semiconductor

C438S455000, C438S482000

Reexamination Certificate

active

06303472

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to fabrication processes for integrated semiconductor devices, and, more particularly, to a technique for cutting trenches in specific areas of a crystalline substrate.
BACKGROUND OF THE INVENTION
The rapid spread and sophistication of portable electronic apparatus commonly using microprocessors and complex monolithically integrated systems has made current consumption critical. That is energy consumption of battery powered portable apparatus is a concern. From a technological point of view, a response to the demand for reduced energy consumption is substantially that of further increasing the density of integration. In other words, as size reduction of individual integrated structures is performed, sub-micron dimensions have become half-micron dimensions. Of course, the scaling down process also includes reducing the supply voltage which permits a significant energy savings.
The scaling down process has strong repercussions on certain processing steps, referred to as the “front end” of the fabrication process. In traditional integration architectures, maintaining a high degree of flatness is fundamental in alleviating the criticality of successive masking steps. Along these lines, isolation areas among the distinct integrated structures may be advantageously realized by cutting trenches in the silicon that are then filled with dielectric materials. Other integration architectures, such as USLI (Ultra Large Scale Integration), may benefit from the possibility of cutting extremely precise and controlled trenches in a silicon monocrystal or in a polysilicon layer.
According to known techniques, such trenches are produced by anisotropic etching through the apertures of a resist mask, typically using Reactive Ion Etching (R.I.E.) techniques. These techniques have the disadvantage of being based on the etching time in the absence of appropriate markers to halt the etching once a predefined depth is reached. Moreover, the use of special gas mixtures of reactive compounds may leave undesired residues on the etched surface.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a more effective way of cutting trenches in a monocrystalline substrate or in a crystalline layer.
This object is fully attained by the process of the invention which includes implanting ions of atomic weight and kinetic energy sufficient to amorphize the crystalline material for a predefined depth in an area defined by an ion implant mask. This is performed while keeping the temperature of the target crystalline material sufficiently low to prevent any appreciable diffusion of the implanted ions in the crystal lattice adjacent to the amorphized region (that is, the region of impact and arrest of ions). Hence, instead of using relatively heavy ions at ambient temperature, it is preferable to use relatively light ions such as He or B ions, at a sufficiently low temperature (i.e. at the boiling temperature of liquefied nitrogen in the vicinity of −196° C.).
The implant dose must be sufficient to completely amorphize the crystalline material in the ion region of arrest (that is, to substantially destroy any appreciable ordered scheme of mutual atomic arrangement) with the consequent creation of a highly stressed region by the incorporation of a massive dose of implanted ions.


REFERENCES:
patent: 3982967 (1976-09-01), Ku et al.
patent: 5374564 (1994-12-01), Bruel
patent: 5416043 (1995-05-01), Burgener et al.
patent: 5494835 (1996-02-01), Bruel
patent: 5804086 (1998-09-01), Bruel
patent: 5877070 (1999-03-01), Goesele et al.
patent: 6020252 (2000-01-01), Aspar et al.
patent: 0 660 140 A1 (1994-12-01), None
patent: 2 211 991 (1989-07-01), None
Q.Y. Tong et al., Low Temp. Si Layer Splitting, p. 126-127, (IEEE) Oct. 1997.*
M. Bruel et al., “Smart Cut”: A Promising New Soi Material Tech., pp. 178-179, (IEEE) Oct. 1995.*
H.Moriceau et al., Cleaning and Polishing as key steps for Smart-Cut, Soi process, pp. 152-153, (IEEE) Oct. 1996.

Affiliated with

Also associated with

Rating

Process for cutting trenches in a single crystal substrate does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for cutting trenches in a single crystal substrate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for cutting trenches in a single crystal substrate will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2607155