Complementary MOS semiconductor device

Details Complementary MOS semiconductor device Complementary MOS semiconductor device

1998-11-12

2001-10-23

Abraham, Fetsum (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S357000, C257S411000, C257S351000, C257S369000

Reexamination Certificate

active

06307234

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a complementary MOS semiconductor device which is suitable for a mobile apparatus, and more particularly to a complementary MOS semiconductor device in which even if gate insulating films of field effect transistors constituting a complementary MOS logic circuit are made less than 2.5 nm in thickness, the power consumption in non-operation is efficiently reduced.
2. Description of the Prior Art
In recent years, the demand for mobile apparatuses has increased. The mobile apparatuses presuppose the outdoor use of personal computers, portable telephones and the like, and the electric power is supplied to the mobile apparatuses by a battery. For this reason, in the mobile apparatuses, it is very important to reduce the power consumption in the non-operation thereof as well as the power consumption in the operation thereof. In addition, as for a semiconductor device for use in the mobile apparatus, in particular, a complementary MOS semiconductor device is effective because the complementary MOS semiconductor device has the lower power consumption in the non-operation thereof.
However, if a threshold voltage of a MOS FET is lowered in order to increase the circuit operating speed of a semiconductor device, the power consumption in non-operation becomes high since a current which is caused to flow in non-operation (hereinafter, referred to as “a stand-by current” for short, when applicable) is increased.
FIG. 4
is a circuit diagram showing a configuration of a circuit which is incorporated in a conventional complementary MOS semiconductor device. The conventional complementary MOS semiconductor device has two-stages inverters INV
11
and INV
12
incorporated therein. The inverter INV
11
includes a p-channel MOS FET P
11
and an n-channel MOS FET N
11
, and the inverter INV
12
includes a p-channel MOS FET P
12
and an n-channel MOS FET N
12
. Each of these MOS FETs P
11
, P
12
, N
11
and N
12
, is a low threshold voltage MOS FET having a low threshold.
In the conventional complementary MOS semiconductor device thus configured, when a signal input to an input terminal IN
11
which is connected to both of a gate of the p-channel MOS FET P
11
and a gate of the n-channel MOS FET N
11
which are provided in the inverter INV
11
is held at a low level, the p-channel MOS FET P
11
is in a conduction state, while the n-channel MOS FET N
11
is in a nonconducting state. In this case, a signal input to the inverter INV
12
is held at a high level so that the p-channel MOS FET P
12
becomes a nonconducting state, while the n-channel MOS FET N
12
becomes a conduction state. Then, a signal at a low level is output through an output terminal OUT
11
which is connected to both of a drain of the p-channel MOS FET P
12
and a drain of the n-channel MOS FET N
12
. At this time, though in the inverter INV
11
, the n-channel MOS FET N
11
is in a nonconducting state, in actual, a large stand-by current is caused to flow resulting from that the MOS FET is of the low threshold voltage type. For this reason, a through current
21
corresponding to this stand-by current is caused to flow through the path extending from a power source line L
11
to a GND line L
12
. In addition, in the inverter INV
12
, a through current
22
corresponding to a stand-by current of the p-channel MOS FET P
12
is caused to flow through the path extending from the power source line L
11
to the GND line L
12
. These through currents
21
and
22
result in the power consumption in non-operation being increased.
Then, the circuit which is designed in order to solve the above-mentioned disadvantage is proposed (refer to Japanese Patent Application Laid-open No. Hei6-29834). The circuit disclosed in this official gazette is designed on the basis of the logic circuit shown in
FIG. 4
, and there is provided therein means for separating the power source line and the GND line from that logic circuit.
FIG. 5
is a circuit diagram showing a configuration of the circuit disclosed in Japanese Patent Application Laid-open No.Hei6-29834. In this connection, in the circuit shown in
FIG. 5
, parts similar to those in the logic circuit shown in
FIG. 4
are denoted by the same reference numerals, and the detailed description thereof is omitted here for the sake of simplicity. In the circuit disclosed in Japanese Patent Application Laid-Open No. Hei 6-29834, a p-channel MOS FET P
13
is provided as a power supply circuit S
11
across a power source line L
13
and a pseudo power source line V
11
, and also an n-channel MOS FET N
13
is provided as a power supply circuit S
12
across a GND line L
14
and a pseudo GND line V
12
. Each of the p-channel MOS FET P
13
and the n-channel MOS FET N
13
is a high threshold voltage MOS FET having a high threshold. Now, a gate of the p-channel MOS FET P
13
is connected to a switch SW
11
through an inverter INV
13
, while a gate of the n-channel MOS FET N
13
is connected directly to the switch SW
11
.
In the conventional circuit configured as described above, if the switch SW
11
is caused to be a nonconducting state in non-operation by the inverters INV
11
and INV
12
, both of the p-channel MOS FET P
13
and the n-channel MOS FET N
13
become a nonconducting state so that both of the inverters INV
11
and INV
12
are separated from the power source line
13
and the GND line
14
. In addition, since each of the p-channel MOS FET P
13
and the n-channel MOS FET N
13
is the high threshold voltage MOS FET, the stand-by current thereof is remarkably thinner than that of the MOS FETS P
11
, P
12
, N
11
and N
12
, and hence the through current which is caused to flow through the path extending from the power source line L
13
to the GND line L
14
is remarkably suppressed. As a result, the power consumption in non-operation is remarkably reduced.
In addition, there is proposed a circuit which is capable of reducing the power consumption in non-operation without reducing the operating speed (refer to Japanese Patent Application Laid-open No. Hei 7-38417). In the circuit disclosed in this official gazette, a first inverter comprised of a MOS transistor having a low threshold voltage and a second inverter comprised of a MOS transistor having a high threshold voltage are provided in a logic circuit. Further, the first inverter is designed in such a way as to be separated from a power source in the non-operation thereof.
According to the circuit disclosed in Japanese Patent Application Laid-open No. Hei 7-38417, during the operation, the high speed switching operation is carried out by the first inverter, while during the non-operation, the output level is held by the second inverter. For this reason, the power consumption in the non-operation can be suppressed to the remarkably low value.
However, there arises the problem that when MOS FETs are shrunk finely along with the promotion of the high speed operation and the high integration of LSIs so that the gate length becomes about 0.1 &mgr;m, in the conventional complementary MOS semiconductor device in which the circuit configured as described above is incorporated, the power consumption thereof in the non-operation is high. In particular, since in an LSI which is operated by a battery, even in the non-operation as well, the remarkably high power consumption is generated and the battery consumption becomes remarkable. In the present circumstances in which the demand for the mobile apparatus is more and more increased, it is very important to solve this problem.
The device parameters such as size and the like of MOS FETs are finely shrunk in accordance with a certain proportional scale down rule. As for the proportional scale down rules, there have been proposed the electric field—definite proportional scale down rule, the voltage—definite proportional scale down rule, the quasi-electric field—definite proportional scale down rule and the like. Then, in any of the proportional scale down rules, it is presupposed to shrink both of the gate length and the

Affiliated with

Also associated with

Rating

Complementary MOS semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Complementary MOS semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Complementary MOS semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2606807