Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1997-08-29
2001-02-13
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S638000, C438S639000
Reexamination Certificate
active
06187660
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electronic circuits, and more particularly relates to high speed electronic circuits propagating high frequency signals.
2. Art Background
Electronic circuits, and in particular computer and instrumentation circuits, have in recent years become increasingly powerful and fast. Driven in large part by customer demand, present day computer circuits are many times, and in cases, several orders of magnitude faster than their prior generation counterparts. When circuit frequencies and signal wave forms are sufficiently low, inductive reactance is small and only the resistance and capacitance of wires is significant. Electronic components may be represented as lumped circuit elements. However, as clock frequencies and the associated propagated signals exceed frequencies of many tens of MHz, inductive reactance increases and capacitance reactance decreases. The electrical wires are more sensitive to the surrounding geometry and structure and are modeled using transmission lines. For example, electrical signals operating at high frequencies, including clock and data signals, emit electric fields from their associated data paths which couple to and affect neighboring signals. In fact, interconnections are becoming the limiting factor in how fast electronic circuits may operate, especially in VLSI (Very Large Scale Integration) and ULSI (Ultra Large Scale Integration) circuits.
In order to enhance the speed and performance of high speed electronic circuits, ground planes are used to improve the propagation of signals along electrical pathways. As suggested above in connection with the surrounding geometry of high frequency signal propagation, ground planes are desirable because they help control the impedance presented to a signal propagating along a wire, thereby reducing crosstalk and reflections. Reflections can be caused by variations in surface topography as a signal path traverses over steps, and other physical boundaries, or by impedance discontinuities along the signal path. Ground planes ensure that reflections in signal data paths from variations in geometry are minimized, and that signal line impedance does not vary substantially as the signal path traverses the circuitry. Further, because the high frequency electric field emitting from a given signal path using a ground plane is concentrated between that signal path and the ground plane, crosstalk between the given signal path and an adjacent signal path is commensurably reduced. Ground planes are frequently incorporated into high frequency electronic circuitry because they are effective in reducing crosstalk and reflections in high frequency signal paths. For example, ground planes are common place in electronic circuits operating at RF and microwave frequencies.
Although known in the prior art, fabrication of ground planes in electronic circuits remains cumbersome, requiring two distinct material deposition steps and two distinct patterning operations. In particular, a ground plane metal would typically be deposited upon a previously deposited dielectric layer, whereafter the ground plane metal is patterned and etched. Thereafter, a second dielectric layer is deposited, patterned, and etched in an appropriate fashion to insulate the ground plane metal. In order to make electrical contact with external control and data signals, metallic conductors that are below the ground plane metal must rise up and pass through the ground plane metallization without making physical contact to it. Where such underlying metallic conductors must pass through the ground plane, it is necessary to electrically insulate the conductor metal from the ground plane metal to prevent shorting. Accordingly, the “double deposition” and “double patterning” methods have been exclusively used in the prior art to insulate the metallic conductor passing through the ground plane metal. Patterning operations are complex in that they typically require a photo-lithographic process and etching process. The added complexity will have an effect on the yield of the product and in turn, the cost.
As will be explained in the following detailed description, the present invention discloses a new ground plane and sidewall insulator structure which may be used to singly or in combination to produce embedded ground planes or, alternatively, shielded conductor signal paths. Moreover, the present invention provides methods requiring fewer processing operations for producing an embedded ground plane using sidewall insulation for interconnections passing through the ground plane.
SUMMARY OF THE INVENTION
Embedded ground plane and shielding structures using sidewall insulators in high frequency electronic circuits using vias and methods for fabricating same are disclosed. In a first preferred embodiment, a first dielectric layer is deposited over a substrate which may comprise underlying circuitry. The underlying circuitry can include a deposited and patterned first metallic conductor layer. The first dielectric layer is deposited on the substrate, followed immediately by the deposition of a ground plane metal and a second insulating dielectric layer. A photo-resist layer is then applied and patterned to define vertical interconnecting vias or contacts. All constituent layers of the embedded ground plane are etched using the defined photo-resist. After the interconnecting vias have been opened using appropriate etching processes, a third insulating dielectric is deposited and anisotropically etched to produce vertically extending sidewall insulators within the previously opened vias or contacts. A second conductor metal is thereafter deposited, patterned, and etched. The second conductor metal fills the vias and forms an interconnected network of metallic conductor signal and power paths joined by vias extending through and insulated from the embedded ground plane. Conducting paths may be alternatively fabricated in other ways including a “plug” process wherein a conducting material fills a via and then, using a separate deposition step, conducting material for the signal and power paths are patterned and etched.
In a second alternative preferred embodiment, the sidewall insulators may be fabricated multiple times to form shielded signal paths. A first dielectric layer is deposited over a substrate which may comprise underlying circuitry. A first insulating dielectric layer is then deposited, followed immediately by the deposition of a first shielding metal and a second insulating dielectric layer. A photo-resist layer is then applied and patterned to define vertical contact openings. All constituent layers of the first shielding metal structure are etched using the defined photo-resist. After the contact openings have been opened using appropriate etching processes, a third insulating dielectric is deposited and anisotropically etched to produce vertically extending sidewall insulators within the previously opened contact openings. A first metallic conductor layer is thereafter deposited, whereafter a fourth insulating dielectric layer is immediately deposited. A second photoresist layer is then applied and patterned to define first layer interconnect traces together with this fourth dielectric layer. Thereafter, a fifth insulating dielectric layer is deposited and subsequently anisotropically etched to produce a second set of vertically extending sidewall insulators adjacent to the lateral edges of the first interconnect metal traces. A second shielding metal layer is next deposited followed immediately by a sixth insulating dielectric layer deposited above the second shielding metal. A third photo-resist layer is applied and patterned to define vertically interconnecting vias. All constituent layers of the second shielding metal structure are etched using the third photo-resist layer. After the interconnecting vias have been opened using appropriate etching processes, a seventh insulating dielectric layer is deposited and thereafter anisotropically etched to produce a third set of vertica
Gurley Lynne A.
Intel Corporation
Kaplan David J.
Niebling John F.
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