Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-11-09
2001-11-27
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240, C365S185290
Reexamination Certificate
active
06324100
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device capable of electrically programming or erasing data and, more particularly, it relates to a memory device to be used for a stacked gate type flash EEPROM in which a negative potential is applied to the control gate for erasing data.
2. Description of the Related Art
Conventionally, hot electrons are injected from the drain into the floating gate of a flash EEPROM with a stacked gate structure for writing or storing data therein. On the other hand, negative and positive electric voltages are respectively applied to the gate and the source of the device to cause a so-called Fowler-Nordheim (F-N) tunneling current to flow from the source for erasing the stored-data.
Methods of manufacturing a flash EEPROM of the above described type have already been disclosed by the inventor of the present invention (Japanese Patent Applications KOKAI Application Nos. 3-186439 and 5-4305).
According to any of these known methods, bias voltages as typically shown in the chart of
FIG. 2
are applied to the transistor (
FIG. 1
) of a memory cell for data storage, read or erasure. Referring to
FIG. 2
, Vsub denotes the electric potential of the substrate which is constantly held to 0V (ground potential), whereas Vg denotes the electric potential of the control gate that varies between −10V (for data erasure) and 12V (for date storage).
However, there is a problem concerning stress voltage as discussed below that needs to be solved for a memory device of the category under consideration before it can meet the demand for extreme down-sizing and high performance that has become so strong in recent years.
a) Voltage Vg (=−10V) to be applied to the gate for erasing data is generated by a negative voltage generating circuit as typically illustrated in
FIG. 3
that is arranged in the substrate of the device. While voltage Vg is available from terminal
0
of the circuit of
FIG. 3
, then potential vn of node N will be reduced to −10−vth (Vn=−10−vth, where Vth is a threshold voltage (approximately 3v) of P-channel type MOS transistor
101
with the gate and the drain connected).
b) If a decoding function is assigned to gate voltage Vg as disclosed in Japanese Patent Application KOKAI Publication No. 5-4305, a stress voltage equal to VSW−VBB (where VSW is the voltage of the power source of the row decoder which is approximately 5V for data erasure and VBB is a negative voltage (e.g. −10V)) is generated in the row decoder.
The stress voltage generated in a substrate makes a serious problem as devices are down-sized, because it is difficult to reduce the electric field required for the flow of an F-N tunneling current in response to the reduced size of the device.
Thus, the problem of a stress voltage generated in the substrate of a memory device of the type under consideration has provided a barrier to be overcome for realizing a small high quality memory device.
SUMMARY OF THE INVENTION
In view of the above identified problem, it is therefore an object of the present invention to provide a nonvolatile semiconductor memory device which is made free from any stress voltage that may be applied to various elements of the device such as transistors located close to the memory cells or a memory device in which data can be erased by an F-N tunneling current with a gate voltage that is lower than ever.
According to the invention, the above object is achieved by providing a nonvolatile semiconductor memory device with a stacked gate structure comprising a semiconductor substrate of a first conductivity type, first and second wells of a second conductivity typeformed in a surface region of the semiconductor substrate, a third well of the first conductivity type formed in the second well, a memory cell formed in the semiconductor substrate, a transistor of the first conductivity type formed in the first well for constituting a peripheral circuit, a transistor of the second conductivity type formed in the third well for constituting the peripheral circuit, and means for controlling the voltages of the semiconductor substrate and the source/drain and the control gate of the memory cell.
The voltage control means operates for data erasure in such a way that it
a) either applies a first power supply voltage vcc (positive voltage) to the semiconductor substrate, a predetermined positive voltage obtained by reducing a second power supply voltage vpp (positive voltage) to the source of the transistor of the memory cell and a predetermined negative voltage to the control gate of the memory cell
b) or applies a power supply voltage Vpp (positive voltage) to the semiconductor substrate and a predetermined negative voltage to the control gate of the memory device.
The voltage control means applies for data storage a predetermined negative voltage to the semiconductor substrate, a predetermined voltage to the source/drain of the memory and a predetermined positive voltage to the control gate of the memory cell.
For the purpose of the invention, since the memory cell is formed within the substrate and the transistors for constituting a peripheral circuit are formed in the wells, the voltage of the substrate can be made variable by providing the substrate with a metal back structure. Thus, if a positive voltage is applied to the substrate for data erasure, the gate may properly operate with a negative voltage much lower than the conventional level to allow the device to be down-sized and show an improved performance.
For a memory device according to the invention, the data storage using channel erasure or substrate hot electrons can be carried out without applying a high voltage to the transistors constituting the peripheral circuit. It also allows the substrate voltage of the memory cell to be held stable when channel hot electrons are injected for data storage.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained means of the instrumentalities and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 4618876 (1986-10-01), Stewart et al.
patent: 4642798 (1987-02-01), Rao
patent: 4879679 (1989-11-01), Kikuda et al.
patent: 4893257 (1990-01-01), Tanaka et al.
patent: 4907058 (1990-03-01), Sekai
patent: 5010520 (1991-04-01), Minagawa et al.
patent: 5022000 (1991-06-01), Terasawa et al.
patent: 5043788 (1991-08-01), Omoto et al.
patent: 5047981 (1991-09-01), Gill et al.
patent: 5051953 (1991-09-01), Kitazawa et al.
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5122985 (1992-06-01), Santin
patent: 5134449 (1992-07-01), Gill et al.
patent: 5157218 (1992-10-01), Santin et al.
patent: 5168335 (1992-12-01), D'Arrigo et al.
patent: 5223451 (1993-06-01), Vemura et al.
patent: 5243559 (1993-09-01), Murai
patent: 5295102 (1994-03-01), McClure
patent: 5295106 (1994-03-01), Jinbo
patent: 5297088 (1994-03-01), Yamaguchi
patent: 5374838 (1994-12-01), Sawada et al.
patent: 5392253 (1995-02-01), Atsumi et al.
patent: 5396459 (1995-03-01), Arakawa
patent: 5402382 (1995-03-01), Miyawaki et al.
patent: 5438542 (1995-08-01), Atsumi et al.
patent: 5506803 (1996-04-01), Jex
patent: 5600592 (1997-02-01), Atsumi et al.
patent: 5619450 (1997-04-01), Takeguchi
patent: 0 525 678 A2 (1993-02-01), None
patent: 0 550 751 A1 (1993-07-01), None
patent: 5-28784 (1993-02-01), None
patent: 6-215591 (1994-08-01), None
T. Nakayama, “A New Decoding Scheme and Erase Sequence for 5V Only Sector Erasable Flash Memory”, 1992 Symposium on VLSI CIrcuit, Jun. 4-6, 1992/Seattle, pp. 22 & 23.
A. Umezawa, “A 5-V Only Operation 0.6-&mgr; Flash EEPROM with Decoder Scheme in Triple-Well Structure”, IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1540-1545.
Jinbo, Toshikatsu et al., “A 5V-Only 16 Mb Flash Memory with Secto
Atsumi Shigeru
Tanaka Sumio
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Le Vu A.
LandOfFree
Nonvolatile semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Nonvolatile semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile semiconductor memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2606284