Figure operation of layout for high speed processing

Details Figure operation of layout for high speed processing Figure operation of layout for high speed processing

1998-06-09

2001-02-13

Lintz, Paul R. (Department: 2768)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C345S182000, C345S423000, C345S504000, C345S504000

Reexamination Certificate

active

06189129

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a layout verifying system for an integrated circuit, and more particularly to a layout verifying system for layout data of a semiconductor integrated circuit which contains a large amount of repetitive figure data.
2. Description of the Related Art
Layout data of a semiconductor integrated circuit is expressed as a set of figures each of which a plurality of polygons are combined. The number of figures of the layout data is generally large, as many as tens of millions. Therefore, a lot of time and computer resources are necessary to process the layout data by a computer.
As one design process which is performed to the layout data of such an integrated circuit, there is layout verification. The layout verification is mainly divided into physical size verification (DRC) and circuit connection verification (LVS). When the layout verification is performed, it is necessary to perform a figure operating process to the layout data which is composed of a plurality of figures. Here, the figure operating process to the figures means a logic summation of the overlapping figures, a logic product between overlapping figures, and/or transformation of a figure such as expansion, and reduction. By performing such a figure operating process, the figure data can be re-formed to internal data which matches the layout verification such as the DRC and the LVS. For this reason, in the layout verifying system, the figure operating process is an extremely important process.
Especially, in the layout data of an integrated circuit such as a DRAM, a portion of the layout data is composed of a plurality of figures, which are arranged repetitively and periodically. Therefore, when a figure operating process is performed to the layout data of the integrated circuit, it is needed that the figure operating process can be performed at high speed to the figures which are arranged repetitively and periodically.
Next, the repetitive figures and the figure operating process will be described below.
For the figures which are arranged repetitively and periodically, it is generally possible to be expressed by a figure data composed of shape data and position data of a figure element as a basic unit and an array data, as shown in
FIGS. 3A and 3B
. The shape data represents the shape of the figure element and the position data represents the position coordinate of the figure element. Such repetitive and periodic figures are referred to as a figure array hereinafter. The array data represents the arrangement pitches between the figure elements in horizontal and vertical directions and arrangement numbers of figure elements in horizontal and vertical directions.
The figure data of the figure array and the array data thereof are stored in a memory in case of computer processing, as shown in FIG.
3
B. This data structure needs only a small memory capacity, compared with the case which data representing figures are distributedly stored in the memory. Thus, when a great deal of figure data are processed, it is very important how many figure data can be manipulated as the figure array.
To perform a figure operating process, a data representing the overlapping between the figures, i.e., an overlap indication, data is necessary in addition to the figure data and the array data. This is expressed as a set of identifications, each of which is allocated for each figure data, as shown in
FIGS. 4A
to
4
D. This data is referred to as an overlap indication data.
An actual figure operating process is performed not to each of the figure data but to a group of figure data for figures which overlap each other. More specifically, the figure data where can be traced in accordance with the overlapping portions are collected into a group. Hereinafter, these groups are referred to as chain groups, as shown in
FIG. 5A
to
5
C by a reference numeral
93
,
94
and
95
, respectively. The results that the figure operating process of logic summation is performed to the chain groups
90
,
91
and
92
are shown in
FIGS. 5A
to
5
C by reference numerals
93
,
94
and
95
, respectively. In this way, when the figure operating process is performed, the inputted figure data must be first grouped into the chain groups based on the overlap indication data and then processed.
A conventional figure processing apparatus for the figure array will be explained with reference to
FIGS. 1
to
8
.
The structure of the conventional figure processing apparatus will be explained with reference to a system block diagram of FIG.
1
. As shown in
FIG. 1
, the conventional figure processing apparatus is composed of an input unit
11
for inputting figure data, a storage unit
12
for storing the figure data and an overlap indication data, a data processing unit
13
for performing a figure operating process to the figure data based on the overlap indication data, and an outputting unit
14
for outputting the processing result. The storage unit
12
is composed of a figure data storage section
15
for storing the figure data, and an overlap indication data storage section
16
for storing the overlap indication data. Also, the data processing unit
13
is composed of an overlap indication data processing section
17
for inputting the overlap indication data to process, a chain group generating section
8
for producing a chain group from the overlap indication data and a figure data operating section
19
for performing a figure operating process for every chain group.
The operation when an figure array is processed by the conventional figure processing apparatus will be described with reference to a flow chart of FIG.
2
.
The figure data is sequentially read from the figure data storage section
12
one by one. Here, the case that the read figure data is for a figure array will be described.
First, a figure array C is read from the figure data storage section
15
by the inputting unit
11
(step S
21
). Next, if the overlap indication data of the figure array C is present (yes in step S
22
), the overlap indication data processing section
17
reads the overlap indication data from the overlap indication data storage section
16
. At this time, as shown in
FIG. 6
, because the figure data A and B are present which can be traced based on the overlap indication data, the figure data C is registered in a chain group in which the figure data A and B have been already registered (step S
23
). In case of the registration of the figure data C, it is determined whether the array data of the figure array C is coincident with the array data of figure arrays A and B (Step S
24
).
If the array data are both coincident with each other, the figure array can be registered in the chain group as it is. However, as shown in
FIG. 6
, when the array data of the figure array C is different from those of the figure arrays A and B, the figure C is not possible to be processed as the same figure array as the figure array A or B. In accordance with, the figure array C must be developed as a plurality of figures. Also, because figures of the chain group are connected to have overlapping portions, all the figures of the figure arrays must be developed when one of the figures of the figure array is developed. If not, the figure operating process can not be performed. This means that the figures of the figure array B are developed based on the figure array C and also the figures of the figure array A are developed based on the figure array B (Steps S
25
and S
26
).
In this manner, the chain group ABC is divided into chain groups E to J, as shown in FIG.
7
. If all the inputted figures are registered on the chain groups (yes in step S
27
), the figure operating process is performed to each of the chain groups (step S
28
).
FIG. 8
shows the result of the logic summation of the figure operating process to the figure arrays A, B and C. Lastly, a figure operating process result is outputted.
The primary problem is in that if a figure array has different array data from already registered fig

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