Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-09-27
2001-10-02
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S711000, C438S723000, C438S724000, C438S743000, C438S744000
Reexamination Certificate
active
06297162
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating semiconductor devices, and more particularly to the use of silicon oxynitride as an etching stop for silicon oxide etching.
(2) Description of the Prior Art
A variety of thin film materials are used in integrated circuit manufacturing. One such thin film is silicon oxynitride (SiON). Silicon oxynitride is a material that is used as an insulator and as a diffusion barrier in some ultra large scale integration (ULSI) processes.
In addition, silicon oxynitride is used as a masking, or etch stop, layer in certain applications. Such uses rely on the relative etch rate of oxynitride when compared to other films. For example, if the proper reactive ion etch chemistry is selected, silicon oxide will exhibit a much higher etch rate than silicon oxynitride under the same etch conditions. This property is called selectivity. In the art, a high selectivity ratio allows a slow etching film type, in this case silicon oxynitride, to act as a mask and an etching stop for a fast etching film type, such as silicon oxide.
This oxide-to-oxynitride selectivity is used in the art to facilitate the etching of self-aligned contacts (SAC) for metal oxide semiconductor (MOS) transistor gates. Referring to
FIG. 1
, a cross section of a partially completed prior art integrated circuit is shown. On a substrate
10
, two MOS transistor gates are shown. Each MOS gate has a gate oxide
14
, polysilicon gate node
18
, and silicon nitride sidewalls
22
. A thin layer of silicon oxynitride
26
is shown overlying the MOS gates. Overlying the silicon oxynitride is an interlevel dielectric
30
(ILD) of silicon oxide.
Because the two MOS gates are very closely spaced, a special type of contact must be formed to connect the surface of the substrate
10
to circuitry above the ILD
30
. A self-aligned contact, or SAC, allows the contact hole to be made wider than the available space between the MOS gates. By using a SAC, a lithography and etch combination can be used to make contacts that are effectively smaller than the processes are capable of producing. The key to the SAC shown is the selectivity of oxide and oxynitride in the oxide dry etch process. By selecting the dry, or plasma, etch chemistry properly, the etch rate of the silicon oxynitride layer
26
can be made sufficiently smaller than that of the ILD oxide layer
30
. When the ILD oxide is etched through to make the contact hole, the oxynitride will act as an etching stop to prevent the plasma etch from damaging the MOS gate or the substrate surface
10
.
FIG.
2
and
FIG. 3
show two potential problems with the conventional art. To achieve ULSI, the minimum space between the two MOS gates must be as small as possible. The silicon oxynitride layer
26
must also be kept very thin. Referring to
FIG. 2
, if the layer is made too thin, however, it will not be sufficiently thick enough to stop the silicon oxide etch and protect the underlying MOS gates. The MOS gates will be damaged
35
by the etch. On the contrary, if the silicon oxynitride
26
is made thicker, this causes problems with gap filling of the ILD film
30
. Referring to
FIG. 3
, voids
40
can form in the ILD layer
30
if the silicon oxynitride layer
26
is too thick relative to the space available between the MOS gates. Additionally, if the silicon oxynitride is formed using a plasma enhanced deposition process, plasma and hydrogen damage to underlying films is increased as the thickness of the silicon oxynitride film increases.
A second prior art application of this type of etch stop is a dual damascene trench as shown in
FIG. 4. A
first dielectric layer
43
is deposited overlying a semiconductor substrate
41
. First conductive traces
42
, typically of copper, are formed in the first dielectric layer
43
. A diffusion barrier layer
44
is deposited overlying the first conductive traces
42
and the first dielectric layer
43
. The diffusion barrier layer
44
also serves as an etching stop. A second dielectric layer
45
is deposited overlying the diffusion barrier layer
44
. An etch stop layer
46
is deposited overlying the second dielectric layer
45
. Finally, a third dielectric layer
47
is deposited overlying the etch stop layer
46
.
As in the previous example, either silicon nitride or silicon oxynitride may be used in this application. Particularly, the diffusion barrier layer
44
and the etch stop layer
46
may be comprised of either silicon nitride or silicon oxynitride. The trench and via etches for the dual damascene structure require an etching stop above the first conductive traces
42
and the second dielectric layer
45
. Again, a trade-off must be made. Silicon nitride has excellent selectivity but a relatively high dielectric constant. Use of silicon nitride will increase the capacitance of dual damascene interconnects. Alternatively, silicon oxynitride exhibits a lower dielectric constant. However, a thicker layer must be used to effectively stop the etch.
Several prior art approaches use silicon oxynitride and nitridized silicon oxide to improve integrated circuit processes. U.S. Pat. No. 5,536,681 to Jang et al teaches a method to improve the gap filling capability of O
3
-TEOS over a plasma enhanced silicon oxide by selectively treating the PE-oxide with N
2
plasma. U.S. Pat. No. 5,766,974 to Sardella et al discloses a technique to eliminate damage to interlevel dielectric due to metal overetch by using an oxynitride layer as a metal etch stop. U.S. Pat. No. 5,198,392 to Fukuda et al teaches a process to form an oxynitride film by nitridizing a previously formed silicon dioxide film with nitrous oxide. U.S. Pat. No. 5,188,704 to Babie et al discloses a two-step process to selectively etch silicon nitride where silicon oxynitride overlies silicon nitride that also overlies silicon oxide.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method to improve the capability of silicon oxynitride as an etch stop for silicon oxide dry etching in the manufacture of integrated circuits.
A further object of the present invention is to provide a method to reduce the etch rate of silicon oxynitride in silicon oxide dry etching by nitridizing the silicon oxynitride.
A still further object of the present invention is to provide a method for improving self-aligned contact processes by nitridizing the silicon oxynitride to reduce the silicon oxynitride etch rate in silicon oxide dry etching.
Another further object of the present invention is to provide a method for improving dual damascene interconnects processes by forming a nitridized silicon oxynitride etch stop.
In accordance with the objects of this invention, a new method to improve the capability of silicon oxynitride as an etching stop in silicon oxide plasma etching is achieved. A semiconductor substrate is provided. Devices, such as MOS transistors, are provided in and on the substrate. A layer of plasma enhanced silicon oxynitride is deposited overlying the desired features and devices. A nitrogen plasma treatment is performed on the silicon oxynitride layer to nitridize the top surface and thereby reduce the etch rate of the silicon oxynitride layer when exposed to a silicon oxide plasma etch environment. A layer of silicon oxide is deposited overlying the silicon oxynitride layer. The silicon oxide layer is plasma etched through to the silicon oxynitride in areas defined by photolithographic process to define contact holes. The silicon oxynitride layer that acted as an etching stop for the oxide etch is then etched to complete the contact holes. A metal layer is deposited overlying the silicon oxide and filling contacts. This metal layer is etched to define connective features. A plasma nitride layer is formed overlying the metal layer and silicon oxide layer. This completes the fabrication of the integrated circuit.
Also in accordance with the objects of this invention, a new method to improve the capability of silicon oxynitride
Chiu Yuan-Hung
Fu Chu-Yan
Jang Syun-Ming
Ackerman Stephen B.
Pike Rosemary L. S.
Saile George O.
Taiwan Semiconductor Manufacturing Company
Tran Binh X.
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