Optimized memory organization in a multi-channel architecture

Details Optimized memory organization in a multi-channel architecture Optimized memory organization in a multi-channel architecture

1998-08-26

2001-10-16

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S170000, C711S171000, C711S172000, C711S165000, C710S057000, C710S120000

Reexamination Certificate

active

06304947

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention generally relates to the memory organization in computer systems with a multi-channel architecture.
FIG. 1
shows a principal arrangement of a computer system
10
with a multi-channel architecture. The computer system
10
comprises a main computer
20
for controlling the computer system
10
, a data storage
30
, and a plurality of individual channels
40
AA, . . . ,
40
ZZ. Each one of the plurality of individual channels
40
AA, . . . ,
40
ZZ comprises an individual channel memory
50
AA, . . . ,
50
ZZ, and is connected via a system bus
60
to a controller
70
for controlling the plurality of individual channels
40
AA, . . . ,
40
ZZ. It is to be understood that the controller
70
can also be part of the main computer
20
, however for the sake of a better understanding, is referred herein as an individual element.
The multi-channel architecture distinguishes from other computer architectures in that the architecture of the computer system
10
allows a functioning of each one of the plurality of individual channels
40
AA, . . . ,
40
ZZ independent of the other channels
40
AA, . . . ,
40
ZZ.
Each one of the plurality of individual channels
40
AA, . . . ,
40
ZZ might comprise an individual processing unit and therefore represent an ‘intelligent’ channel. The main computer
20
represents a ‘central intelligence’ of the computer system
10
and may control the plurality of individual channels
40
AA, . . . ,
40
ZZ to a certain extent by means of the controller
70
.
The data storage
30
can be any storage as known in the art, however, in most cases represents a ‘central storage’ of the computer system
10
and is therefore in general a slower but larger storage medium than the ‘decentralized’ channel memories
50
AA, . . . ,
50
ZZ. The data storage
30
normally is a disk storage, whereas the channel memories
50
AA, . . . ,
50
ZZ might be silicon memories such as a RAM (random access memory), a DRAM (dynamic random access memory), or an SDRAM (synchronous dynamic random access memory).
It is also to be understood, that the computer system
10
may also comprise a plurality of individual channels without respective channel memories. However, since those channels make no contribution to the memory organization in the multi-channel architecture, they are disregarded herein for the sake of simplicity.
The plurality of individual channels
40
AA, . . . ,
40
ZZ can be connected with inputs and/or outputs of other devices and provide data thereto and/or receive data therefrom. However, since those devices also make no contribution to the memory organization in the multi-channel architecture, they are accordingly disregarded herein for the sake of simplicity.
FIG. 2
shows a principal arrangement of another embodiment of the computer system
10
with a multi-channel architecture. The arrangement of
FIG. 2
differs from the arrangement of
FIG. 1
in that one or more of the plurality of individual channels
40
AA, . . . ,
40
ZZ according to
FIG. 1
might be physically arranged on one or more channel boards
100
A, . . . ,
100
Z. In the example of
FIG. 2
, channel board
100
A contains channels
40
AA, . . . ,
40
AZ, and channel board
10
OZ contains channels
40
ZA, . . . ,
40
ZZ. It is clear that the actual arrangement of the channels
40
AA, . . . ,
40
ZZ and channel boards
100
A, . . . ,
100
Z depends on the actual application.
The channels
40
AA, . . . ,
40
ZZ are connected within the respective channel boards
100
A, . . . ,
100
Z via a respective channel board bus
110
A, . . . ,
100
Z, which also provides a connection with the system bus
60
. In the example of
FIG. 2
, the channels
40
AA, . . . ,
40
AZ are connected within the channel board
100
A and to the system bus
60
via channel board bus
110
A, and the channels
40
ZA, . . . ,
40
ZZ are connected within the channel board
100
Z and to the system bus
60
via channel board bus
110
Z.
The system bus
60
and the channel board busses
110
A, . . . ,
110
Z are generally embodied as relatively high speed busses, especially in comparison to the connection between the main computer
20
and the controller
70
. The system bus
60
and the channel board busses
110
A, . . . ,
110
Z can be physically and electrically separated by suitable means as known in the art, and are generally controlled by the controller
70
.
An important application of the multi-channel architecture is in testing applications, e.g. for testing integrated circuits (IC's) or other electronic devices, such as the Hewlett-Packard HP 83000 Digital IC Test Systems. A typical testing unit comprises a tester circuit and a device under test (DUT), which can be an IC or any other electronic device. The tester circuit generally comprises a signal generating unit for generating and applying a stream of stimulus data to the DUT, a signal receiving unit for receiving a response on the stream of stimulus data from the DUT, and a signal analyzing unit for comparing the response with an expected data stream. Test data applied to the DUT is also called vector data or test vector and comprises one or more single individual vectors. Each individual vector may represent a signal state which is either to be applied at one or more inputs of the DUT or output by the DUT, at a given point in time.
A specific tester architecture following the multi-channel architecture of
FIG. 1
is the so-called tester-per-pin or test-processor-per-pin architecture, wherein one of the plurality of individual channels
40
AA, . . . ,
40
ZZ is provided for each testable pin of the DUT. The tester-per-pin architecture can be applied in a mono-site architecture, wherein only one DUT can be tested at once, or in a multi-site architecture, wherein a plurality of DUTs can be tested simultaneously and in parallel.
There are several testing methods known in the art to apply test data to the DUT. In a so called ‘parallel test’, the DUT input signal is applied at the inputs of the DUT and the outputs thereof are observed. During a SCAN test, states internal of the DUT can be sequentially changed and/or monitored directly. DUTs that allow SCAN test normally need special storage devices which can be written or read in a serial fashion. Boundary SCAN test is often used during a board test to directly change and monitor certain states at the boundaries of the DUTs on a board.
In certain applications of the computer system
10
, such as testing applications, it might be required that one or more channels of the plurality of individual channels
40
AA, . . . ,
40
ZZ provide a data stream, e.g. of sequential data, which should be preferably without interrupts. In that case, the respective one(s) of the channel memories
50
AA, . . . ,
50
ZZ are loaded, e.g. sequentially, with a certain amount of data, which then again is output by the respective channel, e.g. to the DUT. It is apparent, that each (re-)loading of the channel memories
50
AA, . . . ,
50
ZZ represents an interruption of the data stream which can be applied from one channel. However, it is also clear that a continuous loading or re-loading of data from the data storage
30
to the channel memories
50
AA, . . . ,
50
ZZ of the individual channels
40
AA, . . . ,
40
ZZ is generally impossible due to a different access speed to the data storage
30
and to the channel memories
50
AA, . . . ,
50
ZZ. Further more, the connection between the main computer
20
and the controller
70
might also represent a ‘bottle-neck’ in the data transfer from the data storage
30
to the channel memories
50
AA, . . . ,
50
ZZ.
In other applications, it might (further) be required that the system bus
60
is used—to a certain period in time—only either for writing or for reading purposes at once. This might particularly be important due to noise reasons in testing applications, since the signals on the system bus
60
can influence the testing results. It is apparent that in those applications, a loading or (re-)loading of the channel memories
50
AA, . . . ,
50

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