Memory device

Details Memory device Memory device

1998-05-20

2001-02-27

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S141000

Reexamination Certificate

active

06194303

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a memory device and a method of fabrication thereof.
BACKGROUND
It is known that resonant tunnelling diodes (RTDs) exhibit a negative differential resistance characteristic which can be used as a memory. A recent review of RTDs given in F. Capasso, S. Sen and F. Beltram in High-Speed Semiconductor Devices edited by S. M. Sze, John Wiley & Sons, New York, 1990. Reference is also directed to EP-A-0297778. A typical RTD consists of a substrate with two overlying charge barriers spaced by a conductive region. Because the layers that make up the barriers and the well are very thin, fabricated on the nanometer scale, the device exhibits quantum conductivity effects and can exhibit different stable states each with a different resistance level. Switching between the states can be achieved by applying a predetermined voltage across the device. However, hitherto, such devices have required the continuous application of a bias voltage to maintain the different resistance states.
In accordance with the invention, there is provided a memory device comprising first and second terminal regions, first and second barrier means disposed between the terminal regions and a conductive region between the first and second barrier means, a dimensional extent of the barrier means and the conductive region being configured to be sufficiently small that the device exhibits first and second relatively high and relatively low stable resistive states in the absence of a voltage applied between the terminal regions.
In accordance with the invention, the memory device can be operated without the requirement for a continuous applied bias voltage.
The values of the resistive states is substantially greater than in the previously reported RTDs. The ratio of the value of the first and second states may lie within a range of 5:1 to 500:1. Typically, the ratio exceeds 250:1 at room temperature, which significantly exceeds a typical comparable value for the prior art of 10:1.
The invention also extends to a method of fabricating the memory device, which includes selectively etching a substrate formed with overlying layers that define the first and second barrier means and the conductive region so as to form pillars at least some of which are of a diameter for exhibiting the relatively high and low conductivity states in the absence of a voltage applied between the terminal regions.
The pillars typically have diameters within a range of 20 to 50 nm.
The first and second barrier means may comprise any suitable double barrier structure and one possible example comprises AlAs/GaAs heterojunctions. The conductive region between the barrier means may comprise a i-GaAs layer.
The etching process may be carried out by evaporating a metallic material such as gold onto the substrate to form a granular layer of discrete islands, and then plasma etching material between the islands so as to form the pillars. A conductive overlayer that bridges the pillars may be provided in order to make contact collectively with the first terminal regions. Connection to the second terminal regions may be achieved through the substrate by means of contact, e.g. AuGeNi that is annealed to the substrate.


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