Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-05-13
2001-10-02
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S421000, C438S422000, C438S319000, C438S411000
Reexamination Certificate
active
06297145
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and more particularly to a semiconductor device that has an air bridge structure, and a method for manufacturing such as semiconductor device.
2. Description of the Related Art
In semiconductor devices, it is important to reduce the as parasitic capacitances between wires. Capacitance between neighboring wires or between upper and lower wires is a cause of a reduction in circuit speed.
In order to reduce parasitic capacitance, the usual method used is that of employing an insulating material having a low dielectric constant as an interlayer insulation film. However, the dielectric constant of an inorganic material that can withstand temperatures of approximately 400° C. is no lower than approximately 3, and with organic materials although there are materials with a dielectric constant of approximately 2, these materials, not being heat resistant, are impractical. For this reason, an air bridge interconnect has been proposed, in which the interlayer insulation film is removed, leaving just the metal interconnect. In this construction, because there is air (having a dielectric constant of 1) between the metal interconnects, it is possible to reduce the parasitic capacitance to the very minimum value. However, if the interconnect becomes long in the floating condition, problems caused by deformation, such as interconnect peeling and shorts caused by interconnect sagging occur.
Because of the above-noted problems, there is disclosed in Japanese Patent No. 2705556 the prevention of deformation of interconnects, by providing supporting posts at a fixed interval beneath a floating metal interconnect.
The above-noted disclosure is described below, with reference made to drawings.
FIG. 13
is a perspective view that shows in conceptual form the above-noted technology, this showing a semiconductor integrated circuit having a two-layer wiring structure. In this device, a silicon substrate
101
has a silicon nitride (Si
3
N
4
) film
102
as a protective layer and etching stopper, a first aluminum interconnect
103
extending in a prescribed direction on top of first post-shaped interlayer insulation film
104
, which are formed by postshaped CVD oxide film
105
that are formed at a uniform pitch, these first post-shaped interlayer insulation film
104
forming an air bridge structure that maintains a prescribed distance with respect to the silicon nitride film
102
. In this case, a silicon nitride film
106
is also formed below the first aluminum interconnects
103
, as an etching stopper.
The second aluminum interconnects
107
, which are formed on top of the first aluminum interconnects
103
extend in a direction that is perpendicular to the first aluminum interconnects
103
and, similar to the first aluminum interconnects
103
, these second aluminum interconnects
107
are maintained at a prescribed distance with respect to the silicon nitride film
102
by second post-shaped interlayer insulation films
108
, which have a film thickness that is greater than that of the first post-shaped interlayer insulation films
104
and which are formed at a uniform interval. In this case, the second post-shaped interlayer insulation films
108
are formed as laminates of the above-noted post-shaped CVD oxide film
105
, a silicon nitride film
106
, and a post-shaped CVD oxide film
109
. In this case as well, a silicon nitride film
110
is provided under the second aluminum interconnects
107
, as an etching stopper.
Therefore, according to the above-noted construction, the first aluminum interconnects
103
and second aluminum interconnects
107
make contact with no elements other than the post-shaped interlayer insulation films
104
and
108
, the surrounding area being a void, so that there is no insulation film between the first aluminum interconnects
103
and the second aluminum interconnects
107
, thereby greatly reducing the wiring capacitance therebetween.
The method of manufacturing the above-noted wiring structure is described below. First, as shown in FIG.
14
(
a
), a silicon nitride film
102
and a CVD oxide film
105
′ are formed on a silicon substrate
101
. Then, as shown in FIG.
14
(
b
), photolithography technology and oxide film etching technology are used to pattern the CVD oxide film
105
′ over the entire chip in a matrix pattern that is skewed by half pitch with the first aluminum interconnects
103
that are to be formed later, thereby forming a matrix CVD oxide film
105
″. Then, a silica film
111
is formed over the entire wafer, the resulting plan-view structure being shown in FIG.
14
(
c
). FIG.
14
(
b
) is a cross-section view along the line A—A that is shown in FIG.
14
(
c
). In order to form the matrix CVD oxide film
105
″ over the entire semiconductor device at a uniform pitch, the silica film
111
is formed uniformly flatly over the entire surface. In this case, it possible to use an applied film such as a polyimide organic film instead of the silica film.
Next, as shown in FIG.
15
(
a
), the applied silica film
111
is baked to cure the film, the resulting flat applied silica film
111
being etched over its entire surface to expose the surface of the matrix CVD oxide film
105
″, after which a silicon nitride film
106
and a first aluminum interconnect layer
103
are formed over the entire surface. At this point, although not shown in the drawing, in the case in which a contact is formed for the purpose of connection between the silicon substrate
101
and the first aluminum interconnects
103
, after growing the silicon nitride film
106
, before forming the first aluminum interconnect layer
103
′, photolithography technology and etching technology are used to form a contact hole in the silicon nitride film
106
and matrix CVD oxide film
105
″ and applied silica film
111
and silicon nitride film
102
. The contact is formed by the growth of the first aluminum interconnect layer
103
′ and the filling of a via hole by tungsten or the like.
Then, as shown in FIG.
15
(
b
), the first aluminum interconnect layer
103
′ is patterned using photolithography and aluminum etching technologies, thereby forming the first aluminum interconnects
103
. FIG.
15
(
c
) is the construction shown in plan view, and FIG.
15
(
b
) is a cross-section view along the line B—B that is shown therein. It can be seen from the above that the first aluminum interconnects
103
are arranged in a vertical direction as shown in the drawings, and extend over the entire surface of the semiconductor device at a uniform pitch, and there is a half-pitch skew with respect to the matrix CVD oxide film
105
″.
Next, as shown by the broken lines in FIG.
16
(
a
), a CVD oxide film
109
′ is grown on the exposed surface of the first aluminum interconnects
103
and silicon nitride film
106
, this having a thickness that is greater than that of the first aluminum interconnects
103
. Then, using the mask that was used to form the matrix CVD oxide film
105
″, photolithography and etching technologies are used to form the second matrix CVD oxide film
109
″, which is on-line overlapped with the matrix CVD oxide film
105
″. Additionally, the silicon nitride film
106
other than the lower part of the first aluminum interconnects
103
and the second matrix CVD oxide film
109
″ is etched, after which an applied silica film
112
is formed and the surface is flattened.
Next, as shown in FIG.
16
(
b
), the entire surface of the applied silica film
112
is etched from above, so as to flatten the second matrix CVD oxide film
109
″. Over this entire surface, a silicon nitride film
110
is formed. FIG.
16
(
c
) is a plan view of the above-noted condition, and FIG.
16
(
b
) is a cross-section view along the direction of line C—C thereof. In the case in which via hole is to be formed for the purpose of connecting t
NEC Corporation
Nguyen Ha Tran
Tsai Jey
Young & Thompson
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