Synchronous audio DRAM storing audio and code data

Details Synchronous audio DRAM storing audio and code data Synchronous audio DRAM storing audio and code data

1999-05-21

2001-12-11

Bragdon, Reginald G. (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C379S067100, C379S088070

Reexamination Certificate

active

06330638

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processing system incorporating dynamic random access memory, particularly to a data processing system incorporating synchronous dynamic random access memory, and more particularly to a data processing system utilizing a synchronous, audio-grade dynamic random access memory for speech and code storage.
2. Description of the Prior Art
In conventional data processing systems, the functionality of the digital signal processor (DSP) is limited by the amount of available high-speed memory. For example, most conventional high-speed DSP cores rely on a zero-wait state internal memory. However, in many cases the cost of this type of device is prohibitive.
Today's embedded DSP designs are based on integrated devices which have zero-wait state memory, with internal ROM (read-only memory) and RAM (random access memory). These zero-wait state memories are required to take advantage of the processing capabilities of these high speed DSPs.
However, in order to meet aggressive cost targets for these embedded DSP designs, the amount of internal memory is severely limited. Consequently, these memory limitations have a tremendous impact on product performance, since software must be optimized to operate with the limited memory available. The end result is fewer features. Memory hungry software algorithms must wait for the next generation IC processing technology to allow the integration of additional memory, while the processing power is already available today.
Moreover, software algorithm development for the embedded DSP designs relies on software development specialists who can create software using particular DSP assembly language. This results in a significant increase in the cost of manufacturing embedded DSPs and associated software.
While higher level language C-compilers are available for today's DSPs to allow software engineers who are not assembly code specialists to develop software for these embedded designs, these C-compilers are not efficient enough to create code which can reside in the limited internal memory of the embedded DSPs. Human intervention is, unfortunately, required.
Dynamically refreshable random access memory (DRAM) is one of a wide variety of integrated circuit memories now available for storing data. Currently, DRAM is often utilized for providing rapid data storage and retrieval in computerized equipment at a reasonable cost.
In response to the tremendous speed increase in the system clock frequency of newer microprocessors, the use of synchronously operated DRAM control circuitry has recently moved to the fore in the rapidly evolving field of DRAM technology. Synchronous DRAM (SDRAM) has several advantages over conventional DRAM and other memory architectures. It is more accurate, and has significantly reduced tendency to misfire from noise on associated control buses.
Additionally, SDRAM is capable of burst addressing and bank switching to achieve very high data transfer speeds. These high speeds are highly desirable for use with today's faster microprocessors, and is motivating the development of improved memory devices.
Synchronous audio-grade random access memory (SARAM) is a memory component which is often produced as a result of the DRAM manufacturing process. These devices, since they typically suffer from failing bits, are not suitable for most computer applications. However, these devices very often have blocks of perfectly good bits, which are suitable for a variety of applications, ranging from simple data storage to critical program storage.
SUMMARY OF THE INVENTION
It has been discovered that a significantly lower cost, higher performance data processing system can be achieved through the incorporation of SDRAM technology, and particularly SARAM technology into today's high speed DSPs.
Accordingly, the present invention provides a high performance data processing system having a low cost, high speed memory that allows a system designer to exploit the speed of the system's digital processor, while simultaneously having virtually unlimited space for operation code. This configuration allows a system designer to take full advantage of a digital processor's high-speed performance, while permitting rapid code development using a higher level language, such as a C-compiler, and further allows for easy software change via an external ROM.
In accordance with a preferred embodiment of the present invention, there is provided a data processing system having a digital processor core, a dynamic RAM, which is preferably a synchronous, audio-grade RAM (SARAM) for speech and code storage, and a separate read-only memory (ROM) for storage of operation code for the DSP core. The system may also use SARAM having one area configured for code space and data, and a second, separate area, which can be used to encode or store speech. The system may also use either a boot mask ROM or erasable programmable ROM. The invention may preferably comprise any devices used for speech recording, such as a telephone answering device, for example.


REFERENCES:
patent: 5600821 (1997-02-01), Falik et al.
patent: 5706334 (1998-01-01), Balk et al.
patent: 5937424 (1999-08-01), Leak et al.
patent: 6108762 (2000-08-01), Law et al.
Cosoroaba, Adrian B., “SDRAM—High Performance Memory Devices Running CPU Bus Speeds”, Proceedings of the IEEE Southeastcon '96, Apr. 1996, pp. 604-607.

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