Structure of a polysilicon plug

Details Structure of a polysilicon plug Structure of a polysilicon plug

1998-10-14

2001-02-13

Saadat, Mahshid (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S349000, C257S377000, C257S547000, C257S620000, C257S621000, C257S754000, C257S755000, C257S757000, C257S758000, C257S774000, C257S775000

Reexamination Certificate

active

06188116

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87112023, filed Jul. 23, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device and, more particularly, to a structure of a polysilicon via of a dynamic random access memory (DRAM).
2. Description of Related Art
A polysilicon via is generally used in a capacitor-over-bit-line (COB) dynamic random access memory (DRAM) to connect a bit line and the source/drain regions on the substrate. Conventionally, a polysilicon via consists of a polysilicon layer and a silicide layer, wherein the polysilicon layer is used to control the resistance over the bit line, wherein the resistance of the bit line is proportional to the thickness of the polysilicon layer of the polysilicon via. Even though having a lower resistance over the bit line provides a better data transmission rate, the thickness of the polysilicon layer of the polysilicon via is usually made to provide a reasonable conductivity while also downsizing the device to fit within a limited space. However, a conventional polysilicon via lacks protection against the occurrence of misalignment in the follow-up photolithography process. That is, the conventional polysilicon via is easily etched through in the presence of misalignment. The conducting layer underneath the polysilicon layer could be damaged by the etching process, and that further causes the occurrence of leakage currents, which degrade the performance of a DRAM cell.
The fabricating process of a conventional polysilicon via is shown in
FIGS. 1A through 1C
.
Referring to
FIG. 1A
, a dielectric layer, of borophosphosilicate glass (BPSG),
30
is deposited on a polysilicon layer
20
by performing a chemical vapor deposition process, wherein the polysilicon layer
20
is formed on a provided substrate
10
. By performing a photolithography process and an anisotropic etching process, a via hole
40
is formed to expose the polysilicon layer
20
.
Referring next to
FIG. 1B
, sequentially, a polysilicon layer
50
and a tungsten silicide layer
60
are both deposited on the BPSG layer
30
and in the via hole
40
by low-pressure chemical vapor deposition processes. The thickness of the polysilicon layer
50
is about 500 to 1000 Å, and the thickness of the tungsten silicide layer
60
is about 1000 to 1500 Å.
Referring to
FIG. 1C
, the tungsten silicide layer
60
and the polysilicon layer
50
are etched to form a bit line
70
and a polysilicon via of a DRAM. Because the polysilicon via is hollow, the width of patterned bit line
70
is wider than the width of the via hole
40
to ensure the conductivity of the bit line
70
. The border layout of the bit line increases the difficulty of the bit-line layout.
Because the polysilicon layer
20
is only covered by the polysilicon layer
50
and the tungsten silicide layer
60
, once a situation of misalignment happens in a follow-up photolithography process, the polysilicon via or the bit line
70
is etched through, which further causes damage to the polysilicon layer
20
underneath. The damage to the polysilicon layer
20
leads to the occurrence of leakage current that degrades the performance and efficiency of a COB DRAM cell.
The width of the bit line
70
on the via hole
40
is made to be wider than the width of the via hole
40
to reduce the damage caused by misalignment. However, the widened bit line on the via hole
40
further increases the difficulty of the layout of a DRAM bit line.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a structure of a polysilicon via to prevent the occurrence of leakage currents, and further simplify the circuit layout.
In accordance with the foregoing and other objectives of the present invention, the invention provides a structure of a polysilicon via that prevents the occurrence of leakage currents in the presence of misalignment in the follow-up photolithography process.
The formation of the structure of a polysilicon via according to the invention mainly includes providing a substrate containing a conducting layer and a dielectric layer thereon, patterning the dielectric layer to form a via hole, filling the via hole with polysilicon to form a via plug, and forming a polysilicon layer and a silicide layer on top of the via plug as a bit line. The via plug is electrically connected to a conducting layer underneath the dielectric layer. The width of the bit line is equal to the width of the via hole. The structure according to the invention can prevent the occurrence of leakage current, and simplify the layout of bit lines as well.


REFERENCES:
patent: 4675715 (1987-06-01), Lepselter et al.
patent: 5281548 (1994-01-01), Prall
patent: 5641991 (1997-06-01), Sakoh
patent: 5796135 (1998-08-01), Liang et al.

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