Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-10-06
2001-11-20
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S302000
Reexamination Certificate
active
06320236
ABSTRACT:
TECHNICAL FIELD
The present invention relates to integrated circuits and fabrication techniques for improving performance and power dissipation. More particularly, the present invention relates to integrated circuits and fabrication techniques that facilitate optimization of the design of unipolar circuit elements, such as FET and MOSFET semiconductors. Even more particularly, the present invention relates to integrated circuits and customized fabrication techniques that facilitate optimization of logic gates using unipolar circuit elements, such as FET and MOSFET semiconductors, by selectively producing asymmetric channel regions in the unipolar circuit elements.
BRIEF SUMMARY OF THE INVENTION
The trend in microelectronic circuitry is to implement new microprocessor logic circuitry which will have increased performance speed, higher density and increased functions with minimal power input. Traditionally the integrated circuit designer must trade-off between speed and power dissipation with the result that the integrated circuit design favors meeting the speed requirements by fabrication of integrated circuits having multiple logic gates rated for functioning at the higher speed without being able to control the power consumption. The type of design employed by the designer to produce the foregoing type of design is known as symmetrical design.
FIGS. 1 and 2
depict the symmetrical design approach for manufacturing a MOS device having the source and drain regions doped symmetrically with concentrations of two dopant impurities D
1
and D
2
. This approach to manufacturing MOS devices has limited applications and is considered adequate to channel lengths in the range of 0.25 &mgr;m.
As the miniaturization of MOS devices continues and the channel lengths become less than 0.25 &mgr;m, the need to customize devices also continues. As a solution, asymmetrical design approaches have been explored. The formation of individual asymmetric channel devices includes using an angled implant of an impurity on the source side of the channel of the device while masking the drain side so that a portion of the implant underlies the gate stack forming a more lightly doped region than the adjacent drain region. Exemplary is the above referenced pending application of one of the applicants of this invention, and the teachings of Odanaka et al., in a paper entitled “Potential Design and Transport Property of 0.1 &mgr;m MOSFET with Asymmetrical Channel Profile”, IEEE Transactions on Electron Devices, Vol. 44, No. 4 (April 1997). Both of these exemplary approaches fail to address the method of producing customized MOS devices with less than 0.25 &mgr;m channel regions on multiple arrangement of MOS devices, such as in a logic gate. Pending application Ser. No. 08/909,044 teaches a particular approach for forming an asymmetrical MOS device on individual MOS devices by angularly implanting an impurity into the substrate at an angle ranging from 5 to 40 degrees. The Odanaka et al. paper teaches using Monte Carlo device simulation and process simulation to analyze device performance and transport property of 0.1 &mgr;m n-MOSFET with asymmetric channel profile.
The benefit of utilizing the asymmetric channel on individual MOS devices is seen to exist for use on multiple arrangements of MOS devices, such as on logic gates. The main benefit in such applications is being able to control roll-off of threshold voltages even though an asymmetric channel device has a channel length in the 0.1 &mgr;m range. Therefore, MOS devices can be densely packaged with the channel width Lg to be equal to the spacing Ls between MOS devices forming the logic gate, (ranging 50-200 nm), see generally FIG.
4
. Additional benefits include being able to form MOS devices having extremely small junction capacitance, for example capacitances on the order of 50 fF (femtofarad), and a benefit of obtaining improved gate delays (20-50 pico-seconds for a 4-input Nand gate having a 50 fFload). Accordingly, a need is seen to exist for a method of optimizing the design of logic gate having multiple MOS devices by expanding upon the basic concept of producing asymmetric channel on single MOS devices. Thus, a primary object of the present invention is to provide a MOS semiconductor structure and process for producing logic gate integrated circuits having asymmetric channel design in each of the logic gate's MOS devices.
BRIEF SUMMARY OF THE INVENTION
Accordingly, the foregoing object is accomplished by providing an integrated semiconductor circuit fabrication method and device comprising at least two MOS transistors forming a logic gate optimized according to a desired device performance speed and packaging density by an asymmetric channel fabrication process. The asymmetric channel fabrication process comprises using a silicon substrate having at least two MOS transistors each having a source and drain region with a channel implant region on the drain side, below the surface of a gate structure, also referred to as a gate stack. The gate stack may comprise a silicon dioxide layer over the silicon substrate and a polysilicon layer over the silicon dioxide layer, or simply a polysilicon layer over the silicon substrate. Variations of either of the foregoing gate stack structures may include the formation of spacers about the gate stack. In one embodiment of the present invention, which is directed to channel implantation on adjacent, odd-even numbered MOS transistors in a logic gate arrangement, a criss-cross, two tilt-angle ion implantation approach is performed on the drain side of the respective channel regions between spaced apart photoresist masked portions of the logic gate. Aside from teaching asymmetric channel implantation on multiple MOS devices, the two tilt-angle ion implantation approach is different from prior methods of forming asymmetric channel designs in that the same photoresist pattern may be used for implanting adjacent MOS devices in the logic gate. Each tilt angle is different and is determined by respective formulas that factor the height of the photoresist mask over the gate stack, the width of the unprotected opening between gate stacks, and width of the gate stack Lg in accordance with the particular MOS device channel being implanted. If heavier doping is desired for a particular channel region, the height of the photoresist mask at that particular channel region may be varied to allow a greater concentration of dopant to reach the channel region. The drain-side of the channel is the preferred side to implant the channel dopant to increase the gate speed. By example, during asymmetric channel fabrication of a two MOS device logic gate fabricated to a stage where the photoresist mask has unprotected openings between gate stacks, a downward, right-to-left orientation of the ion beam would be employed to implant a drain-side of a channel region of the leftmost MOS device, while a downward, left-to-right implantation would be employed for the rightmost MOS device. Additionally, since the height of the photoresist is one variable for determining the tilt angle, photoresist patterns having different heights produce different concentration of channel dopant that impact the speed of the gate and the off-state leakage current. Further, the tilt angle implantation and photoresist masking may be employed on horizontal or vertical orientations of the substrate. Simulation results show that logic gates formed with asymmetric channel transistors having a gate spacing equal to twice the length of the channel length, (Ls=2Lg), yield a 45% improvement in gate delay over symmetric channel devices. Also, if the gate spacing is set to equal to the length of the channel length, (Ls=Lg), logic gates formed with asymmetric channel transistors yield a 230% improvement in gate delay compared to conventional device logic designs. If a photoresist pattern is formed having a large spacing between transistors, more channel dopant is implanted which results in improved off-state leakage. Further, and as another embodiment of
Krivokapic Zoran
Milic Ognjen
Advanced Micro Devices , Inc.
Johnson C.
LaRiviere Grubman & Payne, LLP
Meier Stephen D.
LandOfFree
Optimization of logic gates with criss-cross implants to... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Optimization of logic gates with criss-cross implants to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Optimization of logic gates with criss-cross implants to... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2600714