Silicon thin film, group of silicon single crystal grains...

Details Silicon thin film, group of silicon single crystal grains... Silicon thin film, group of silicon single crystal grains...

1997-05-21

2001-02-20

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S150000, C438S166000, C438S486000, C438S487000, C438S488000, C438S489000

Reexamination Certificate

active

06190949

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a new silicon thin film, a group of silicon single crystal grains, and formation processes thereof, and a semiconductor device, a flash memory cell, and fabrication processes thereof.
A silicon thin film composed of a group of silicon single crystal grains formed on a base body has been used for various kinds of semiconductor devices such as a thin film transistor (hereinafter, referred to as a “TFT”) and a semiconductor device based on a SOI (Silicon On Insulator) technique, and for solar cells; and it is being examined to be applied to production of micromachines.
In the field of semiconductor devices, for example, a stacked SRAM using TFTs as load elements has been proposed. TFTs have been also used for LCD (Liquid Crystal Display) panels. And, in general, a silicon thin film composed of a group of silicon single crystal grains is used for a TFT required to be enhanced in electric characteristics such as a carrier mobility (&mgr;), conductivity (&sgr;), on-current characteristic, subthreshold characteristic, and on/off current ratio. Concretely, efforts are being made to improve characteristics of SRAMs and TFTs by increasing sizes of silicon single crystal grains in combination with reduction in density of twin crystals for lowering a trap density in the silicon single crystal grains.
The enlargement in size (up to 1 &mgr;m) of silicon single crystal grains for improving the electric characteristics of such a silicon thin film has been examined by a SPC [Solid Phase Crystallization, solid phase crystallization from amorphous silicon) technique or an ELA (Excimer Laser Anneal, liquid phase crystallization using excimer laser). One process of forming a silicon thin film using the ELA technique has been known, for example, from a document [“Dependence of Crystallization Behaviors of Excimer Laser Annealed Amorphous Silicon Film on the Number of Laser Shot”, B. Jung, et al., AM-LCD 95, PP. 177-120]. This document describes that a silicon thin film composed of silicon single crystal grains whose selected orientation is approximately the <111> direction can be formed by repeatedly irradiating excimer laser beams on an amorphous silicon layer. Another process of forming a silicon thin film using the ELA technique has been also known, for example, from a document [“Crystal forms by solid-state recrystallization of amorphous Si film on SiO
2
”, T. Noma, Appl. Phys. Lett. 59 (6), Aug. 5, 1991, pp. 653-655]. This document describes that silicon single crystal grains are oriented in the <110> direction, and they include fine {111} twin crystals.
A process of forming a silicon thin film by graphoepitaxial growth using a strip-heater has been known, for example, from a document [Silicon graphoepitaxy using a strip-heater oven”, M. W. Geis, et al., Appl. Phys. Lett. 37(5), Sep. 1, 1980, pp. 454-456]. This document describes that a silicon thin film formed on SiO
2
is composed of a (100) aggregation structure.
A silicon thin film composed of a group of silicon single crystal grains has been also formed by a chemical-vapor deposition (CVD) process or a random solid-phase growth process. For example, the formation of polysilicon crystal grains by CVD has been known from Japanese Patent Laid-open Nos. Sho 63-307431 and Sho 63-307776. In the techniques disclosed in these documents, the selected orientation of silicon single crystal grains is the <111> direction. Incidentally, in the case where a silicon thin film composed of a group of silicon single crystal grains having large sizes is formed by a normal chemical vapor deposition process, it cannot satisfy a uniform quality, a reduced leak, and a high mobility. In the random solid-phase growth process, it is possible to form a silicon thin film composed of a group of silicon single crystal grains having an average grain size of 1 &mgr;m or more; however, it is difficult for silicon single crystal grains to selectively grow. Further, in the TFT using the silicon thin film formed by such a process, since grain boundaries tend to be present in a TFT active region, there occurs a problem that TFT characteristics are varied depending on the presence of the grain boundaries, to thereby shorten the life time of the TFT.
In all of the techniques disclosed in the above-described references, no attempt has been made to regularly arrange a group of silicon single crystal grains on an insulating film. If a group of silicon single crystal grains can be regularly arranged on an insulating film, the TFT characteristics can be highly controlled and equalized, and also one TFT can be formed in each of the silicon single crystal grains. This is expected to further develop the SOI technique.
A process of arranging silicon nuclei or crystal nuclei at desired positions and forming silicon single crystal grains having large sizes on the basis of the silicon nuclei or crystal nuclei has been known, for example, from Japanese Patent Laid-open Nos. Hei 3-125422, Hei 5-226246, Hei 6-97074, and Hei 6-302512. In the technique disclosed in Japanese Patent Laid-open No. Hei 3-125422, micro-sized silicon nuclei or crystal nuclei must be formed by patterning using a lithography process; however, there is a limitation to accurately form these micro-sized silicon nuclei or crystal nuclei by the present lithography technique. In the case where the sizes of silicon nuclei or crystal nuclei are large, polycrystals tend to be formed with twin crystals and dislocations easily produced, resulting in the reduced throughput. In the techniques disclosed in Japanese Patent Lid-open Nos. Hei 5-226246, Hei 6-97074, and Hei 6-302512, it is necessary to irradiate an energy beam enabling fine convergence and direct scanning onto an amorphous silicon layer or to carry out ion implantation. Accordingly, these techniques have problems that not only the step of forming silicon single crystal grains is complicated, but also it takes a lot of time to form silicon single crystal grains because of the necessity of a solid phase growth step, resulting in the reduced throughput.
On the other hand, non-volatile memories are being extensively developed at present. In particular, a flash memory having a floating gate structure is being examined from the viewpoint of the reduced size of the memory cell and the lowered voltage. In a flash memory, data is written or erased by injecting or discharging an electric charge into or from the floating gate. Of various electric charge injecting methods, a channel hot electron injection method or a method of allowing a Fowler-Nordheim's tunnel current to flow by applying a high electric field (for example, 8 MV/cm or more) on a tunnel oxide film are generally used.
In such a flash memory cell, it has been known that a threshold voltage after erasion of data is varied depending on variations in sizes of polycrystalline silicon grains forming a floating gate, for example, from a document [“Non-volatile Memory and Its Scaling”, Journal of Japan Society of Electron Information Communication, Vol. 9, No. 5, pp. 469-484 (May, 1996)]. Further, as one means for realizing a future fine flash memory cell operated at a low voltage, a flash memory including a floating gate composed of silicon nanocrystals has been proposed in a document [“A silicon nanocrystal based memory”, S. Tiwari, et al., Appl. Phys. Lett. 68 (10), 4, pp. 1377-1379, Mar. 4, 1996]. Additionally, as one form of a non-volatile memory to lead the next generation over the present semiconductor device, a single electron memory operated at a low voltage using a small storage electric charge (electron) has been proposed in a document [“A Room-temperature Single-Electron Memory Device Using Fine-Grain Polycrystalline Silicon”, K. Yano, et. al., IEDM93, PP. 541-544].
To realize a flash memory cell hard to be varied in a threshold voltage after erasion of data, it is necessary to make as small as possible variations in sizes of silicon crystal grains formin

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