Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-02-18
2001-02-27
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S347000
Reexamination Certificate
active
06194763
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and more particularly to an insulated gate field effect transistor having an SOI (silicon on insulator) structure.
An SOI-MOSFET (silicone on insulator—metal oxide semiconductor field effect transistor) formed on a thin single crystalline silicone layer on an insulated substrate can be integrated on a large scale on one substrate using a micro fabrication process for silicon. Furthermore, the SOI-MOSFET is suitable for high speed operation because the parasitic capacity of a formed transistor is smaller than that when a conventional single crystalline silicon substrate is used, so that it has been noticed.
A semiconductor device (MOSFET) using a conventional single crystalline silicon substrate biases the channel unit using a substrate electrode. On the other hand, the SOI-MOSFET cannot bias from the lower part of the channel because there is the insulated layer (or insulated substrate) at the bottom of the thin single crystalline silicon layer and there is a problem imposed that it is called a “floating substrate” causing an unstable operation.
Namely, it is reported that the NMOS (N channel MOS) generates a large leakage current in the off state because holes are accumulated in the channel unit and causes a kink (kink effect) in the current characteristic even in the on state. It is known that this problem appears remarkably in an NMOS having a large impact ionization.
An art for solving this problem is disclosed, for example, in Japanese Patent Application Laid-Open 4-34980 and Japanese Patent Application Laid-Open 7-273340.
As described in IEEE Electron Devices Letters, Vol. 15, No. 12, pp. 510 to 512, December 1994, it is considered to bias the channel unit (P-silicon) via the gate electrode. The MOSFET having a structure that the substrate and gate are connected can be regarded as a device in which a FET and a lateral bipolar transistor coexist. It is reported that by such a MOSFET, a characteristic which is excellent particularly in low voltage operation (0.6 V max.) can be obtained.
FIG. 22
is a plane schematic layout showing the device structure disclosed in the aforementioned reference. The plane layout uses the same layout as that of the MOSFET formed on a conventional single crystalline silicon substrate. The characteristic of this structure is that a part of an active region
100
comprising a thin single crystalline silicon layer is patterned in the same shape as that of a gate (electrode)
500
. At a contact
600
of the gate, the gate
500
and the active region are in contact with each other by wiring at the same time.
FIG. 23
shows only the active region
100
shown in FIG.
22
and at the contact portion of the gate, the active region is patterned in a so-called dog bone shape. The cross sectional structure of the contact is shown in FIG.
24
. The cross sectional structure shown in
FIG. 24
is a cross sectional view of the section A—A. As shown in
FIG. 24
, the contact between the gate
500
and the active region
100
is realized by forming a contact hole piercing through the gate
500
and an oxide film
910
of the gate, allowing the active region
100
under the gate oxide film
910
to expose, and forming a metallic wire
700
in the contact hole.
SUMMARY OF THE INVENTION
With respect to the art disclosed in the aforementioned reference, when the active region is to be processed, it is necessary to form a minute pattern in accordance with the gate beforehand. When the contact is to be formed, it is necessary to perform a process of piercing through the gate and to stop the process so as to prevent piercing through the thin silicon layer. It is also necessary to perform contact with the gate on the gate layer side (the inner wall of the contact hole). As a result, a problem of processing arises that no consistency with the ordinary MOS transistor process (the process for forming a MOS transistor on a conventional single crystalline substrate) can be realized and the art is not suited to integration.
Therefore, it is necessary to solve the problem of floating substrate without performing a special process.
An object of the present invention is to provide a semiconductor device having a new SOI structure for giving an electrical potential to the channel forming region.
Another object of the present invention is to provide a semiconductor integrated circuit device having a plurality of insulated gate field effect transistors having a new SOI structure for giving an electrical potential to the channel forming region which are formed on a support substrate.
Still another object of the present invention is to provide a manufacturing method of a semiconductor device having a new SOI structure for giving an electrical potential to the channel forming region.
According to the semiconductor device of the present invention, in a semiconductor device including a single crystalline semiconductor layer mounted on an insulator and an insulated gate field effect transistor having a gate, a source, and a drain electrode which are formed on the single crystalline semiconductor layer, the gate electrode has a 2-layer structure of an upper gate layer and a lower gate layer and the upper gate layer is electrically connected to the channel forming region of the insulated gate field effect transistor.
According to the present invention, the substrate is biased via the gate electrode, so that the problem of floating substrate can be avoided.
As the explanation of the forming process which will be described later shows obviously, the structure of the present invention is realized on a self-alignment basis. Therefore, it is obvious that a problem that no alignment can be realized due to the process of the prior art will not arise.
Namely, the lower gate electrode is processed by continuous etching up to the SOI layer (the single crystalline semiconductor layer) and the side of the SOI layer is exposed. By this processing, the side for contact between the gate and the SOI layer (that is, the channel forming region) is formed. By depositing the upper gate layer on the lower gate layer, the lower gate layer and the SOI layer are automatically connected at the sides thereof.
REFERENCES:
patent: 3974515 (1976-08-01), Ipri et al.
patent: 4996574 (1991-02-01), Shiraski
patent: 5115289 (1992-05-01), Hisamoto et al.
patent: 5381029 (1995-01-01), Eguchi et al.
patent: 6060750 (2000-05-01), Hisamoto et al.
patent: 4-34980 (1992-02-01), None
patent: 7-273340 (1995-10-01), None
Assaderaghi et al., “A Dynamic Threshold Voltage MOSFET (DTMOS) for Very Low Voltage Operation”, IEEE Electron Device Letters, vol. 15, No. 12, Dec. 1994.
Hisamoto Dai
Sudou Yoshimi
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Ngo Ngan V.
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