Pseudo-static leakage-tolerant register file bit-cell circuit

Details Pseudo-static leakage-tolerant register file bit-cell circuit Pseudo-static leakage-tolerant register file bit-cell circuit

2000-12-08

2001-11-20

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including specified plural element logic arrangement

C365S189080, C365S230050

Reexamination Certificate

active

06320795

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to semiconductor devices and, more particularly, to semiconductor memory devices.
BACKGROUND OF THE INVENTION
An ongoing trend in the integrated circuit (IC) industry is to continuously reduce the physical size of ICs. This reduction in size is often achieved by device scaling where each of the dimensions of a circuit are reduced by a predetermined amount to create a smaller circuit having the same or similar operating characteristics as the original circuit. Device scaling, however, has resulted in an increase in sub-threshold leakage currents within circuits using field effect transistors, particularly insulated gate field effect transistors (IGFETs) (e.g., metal-oxide-semiconductor field effect transistor (MOSFETs)). This increased leakage can have a negative impact on circuit robustness, particularly in circuits utilizing wide OR dynamic gate structures (e.g., register files). One technique for improving the robustness of such circuits is to utilize higher threshold voltage (V
T
) transistors within the IC that are less likely to leak when the transistors are in an “off” condition. The use of high V
T
transistors, however, will typically cause a significant reduction in performance in an IC. As can be appreciated, such performance penalties are generally undesirable.


REFERENCES:
patent: 5481495 (1996-01-01), Henkels et al.
patent: 6038193 (2000-03-01), Wang et al.
patent: 6215694 (2001-04-01), Li et al.

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