Method for manufacturing leadless semiconductor chip package

Details Method for manufacturing leadless semiconductor chip package Method for manufacturing leadless semiconductor chip package

1999-11-22

2001-11-06

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C438S111000, C438S123000, C257S666000, C257S667000

Reexamination Certificate

active

06312976

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to an electronic device, and more particularly to a leadless semiconductor chip package and a manufacturing method thereof, wherein a semiconductor die is encapsulated by a plastic package body in a manner that the backside surface of the die is exposed through the plastic package body.
2. Description of the Related Art
FIG. 1
depicts a conventional semiconductor chip package including a lead frame for supporting a semiconductor die
100
. The lead frame includes a plurality of leads having outer lead portions
106
and inner ends
107
. The die
100
is attached onto a die pad
111
by means of a silver paste
114
. The die pad
111
is connected to the lead frame by several supporting bars (not shown in FIG.
1
). The outer lead portions
106
are used for electrical coupling to an outside circuit. The die
100
has bonding pads
117
electrically interconnected to the inner ends
107
of the lead frame though bonding wires
115
. The die
100
, the die pad
111
, the inner ends
107
of the lead frame and bonding wires
115
are encapsulated in a plastic package body
116
made of insulating material such as epoxy.
Because the plastic package body
116
completely surrounds the die
100
, the heat generated from the die
100
during normal operation must pass through the package body
116
to outside. Due to the insulating properties of the package body
116
, heat dissipation from the die
100
is resisted, thereby creating, in some instances, high temperatures within the conventional package which might impair or damage the die
100
.
Therefore, the semiconductor industry develops a leadless semiconductor chip package
200
(as shown in
FIG. 2
) mainly comprising a die
210
disposed on a die pad
220
of a lead fame. The lead frame comprises a plurality of leads
230
electrically connected to the die
210
through a plurality of gold wires
240
. The die and the lead frame are enclosed in a package body
250
wherein the lower surface of the lead frame is exposed through the package body
250
. Consequently, the heat generated from the semiconductor die during normal operation can be directly transferred through the die pad
220
of the lead frame to outside thereby enhancing the thermal performance of the leadless semiconductor chip package
200
. However, since the lower surface of the lead frame is exposed through the package body, flash problems tend to occur at the edge
220
a
of the die pad
220
and the edge
230
a
of the leads
230
, which may be fatal to the solder joint reliability thereof.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to provide a method for manufacturing a leadless semiconductor chip package which utilizes a film to reduce the occurrence of flash during the encapsulation process.
It is a secondary object of the present invention to provide a method for manufacturing a leadless semiconductor chip package which utilizes a tapered lead frame cooperating with a film to further prevent the formation of flash during the encapsulation process.
It is another object of the present invention to provide a method for manufacturing a leadless semiconductor chip package which utilizes a lead frame with notches at the to-be-punched positions thereof to make the singulation process more convenient and correct.
A method of manufacturing a leadless semiconductor chip package in accordance with the present invention comprises the steps of: (A) attaching a semiconductor die onto a die pad of a lead frame, wherein the lead frame comprises a plurality of leads arranged about the periphery of the die pad and each lead has a notch formed at the to-be-punched position thereof; (B) wire bonding the inner ends of the leads to bonding pads on the semiconductor die; (C) sucking a film against a lower part of a molding die, wherein the upper part of the molding die has a cavity; (D) closing and clamping the molding die in a manner that the semiconductor die is positioned in the cavity and the lead frame is disposed against the film; (E) transferring a hardenable molding compound into the cavity; (F) hardening the molding compound; (G) unclamping and opening the molding die to take out the molded product; and (H) punching the molded product in a manner that the punching line is corresponding to the notches of the leads. The lower surface of each lead of the lead frame according to the present invention is smaller than the upper surface thereof such that each lead has a tapered profile.
In the method of manufacturing a leadless semiconductor chip package in accordance with the present invention, the to-be-molded semiconductor die and lead frame is placed on the film sucked against the lower part of the molding die during the encapsulation process. Since the film is made of heat-resistant and elastic material, it provides good sealing such that flash is prevented from forming on the lower surface of the leadless semiconductor chip package, thereby assuring the solder joint solderability. Further, each lead of the lead frame in accordance with the present invention has a tapered profile which cooperates with the film to provide better sealing effect thereby further preventing the formation of flash.
Since the lead frame in accordance with the present invention has notches formed at the to-be-punched positions thereof, the molded product can be punched along the notches of the lead frame thereby making the singulation process more convenient and correct.


REFERENCES:
patent: 5891384 (1999-04-01), Miyajima
patent: 5891483 (1999-04-01), Miyajima
patent: 6081029 (1999-02-01), Yamaguchi

Affiliated with

Also associated with

Rating

Method for manufacturing leadless semiconductor chip package does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing leadless semiconductor chip package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing leadless semiconductor chip package will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2595776